intel: Use the CHIPSET macro in the PCI ID tables for the device name.

Putting the human readable device names directly in the PCI ID list
consolidates things in one place.  It also makes it easy to customize
the name on a per-PCI ID basis without a huge code explosion.

Based on a patch by Kristian Høgsberg.

v2: Fix 830M/845G names and #undef CHIPSET (caught by Emit Velikov).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

3 files changed, 110 insertions, 110 deletions

diff --git a/include/pci_ids/i915_pci_ids.h b/include/pci_ids/i915_pci_ids.h
index 964b1cb4ff0..7d51975c3a8 100644
--- a/include/pci_ids/i915_pci_ids.h
+++ b/include/pci_ids/i915_pci_ids.h
@@ -1,15 +1,15 @@
-CHIPSET(0x3577, I830_M)
-CHIPSET(0x2562, 845_G)
-CHIPSET(0x3582, I855_GM)
-CHIPSET(0x2572, I865_G)
-CHIPSET(0x2582, I915_G)
-CHIPSET(0x258A, E7221_G)
-CHIPSET(0x2592, I915_GM)
-CHIPSET(0x2772, I945_G)
-CHIPSET(0x27A2, I945_GM)
-CHIPSET(0x27AE, I945_GME)
-CHIPSET(0x29B2, Q35_G)
-CHIPSET(0x29C2, G33_G)
-CHIPSET(0x29D2, Q33_G)
-CHIPSET(0xA011, IGD_GM)
-CHIPSET(0xA001, IGD_G)
+CHIPSET(0x3577, I830_M,   "Intel(R) 830M")
+CHIPSET(0x2562, 845_G,    "Intel(R) 845G")
+CHIPSET(0x3582, I855_GM,  "Intel(R) 852GM/855GM")
+CHIPSET(0x2572, I865_G,   "Intel(R) 865G")
+CHIPSET(0x2582, I915_G,   "Intel(R) 915G")
+CHIPSET(0x258A, E7221_G,  "Intel(R) E7221G (i915)")
+CHIPSET(0x2592, I915_GM,  "Intel(R) 915GM")
+CHIPSET(0x2772, I945_G,   "Intel(R) 945G")
+CHIPSET(0x27A2, I945_GM,  "Intel(R) 945GM")
+CHIPSET(0x27AE, I945_GME, "Intel(R) 945GME")
+CHIPSET(0x29B2, Q35_G,    "Intel(R) Q35")
+CHIPSET(0x29C2, G33_G,    "Intel(R) G33")
+CHIPSET(0x29D2, Q33_G,    "Intel(R) Q33")
+CHIPSET(0xA011, IGD_GM,   "Intel(R) IGD")
+CHIPSET(0xA001, IGD_G,    "Intel(R) IGD")
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index fb171daad26..9e30fe2e832 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -1,93 +1,93 @@
-CHIPSET(0x29A2, I965_G)
-CHIPSET(0x2992, I965_Q)
-CHIPSET(0x2982, I965_G_1)
-CHIPSET(0x2972, I946_GZ)
-CHIPSET(0x2A02, I965_GM)
-CHIPSET(0x2A12, I965_GME)
-CHIPSET(0x2A42, GM45_GM)
-CHIPSET(0x2E02, IGD_E_G)
-CHIPSET(0x2E12, Q45_G)
-CHIPSET(0x2E22, G45_G)
-CHIPSET(0x2E32, G41_G)
-CHIPSET(0x2E42, B43_G)
-CHIPSET(0x2E92, B43_G1)
-CHIPSET(0x0042, ILD_G)
-CHIPSET(0x0046, ILM_G)
-CHIPSET(0x0102, SANDYBRIDGE_GT1)
-CHIPSET(0x0112, SANDYBRIDGE_GT2)
-CHIPSET(0x0122, SANDYBRIDGE_GT2_PLUS)
-CHIPSET(0x0106, SANDYBRIDGE_M_GT1)
-CHIPSET(0x0116, SANDYBRIDGE_M_GT2)
-CHIPSET(0x0126, SANDYBRIDGE_M_GT2_PLUS)
-CHIPSET(0x010A, SANDYBRIDGE_S)
-CHIPSET(0x0152, IVYBRIDGE_GT1)
-CHIPSET(0x0162, IVYBRIDGE_GT2)
-CHIPSET(0x0156, IVYBRIDGE_M_GT1)
-CHIPSET(0x0166, IVYBRIDGE_M_GT2)
-CHIPSET(0x015a, IVYBRIDGE_S_GT1)
-CHIPSET(0x016a, IVYBRIDGE_S_GT2)
-CHIPSET(0x0402, HASWELL_GT1)
-CHIPSET(0x0412, HASWELL_GT2)
-CHIPSET(0x0422, HASWELL_GT3)
-CHIPSET(0x0406, HASWELL_M_GT1)
-CHIPSET(0x0416, HASWELL_M_GT2)
-CHIPSET(0x0426, HASWELL_M_GT3)
-CHIPSET(0x040A, HASWELL_S_GT1)
-CHIPSET(0x041A, HASWELL_S_GT2)
-CHIPSET(0x042A, HASWELL_S_GT3)
-CHIPSET(0x040B, HASWELL_B_GT1)
-CHIPSET(0x041B, HASWELL_B_GT2)
-CHIPSET(0x042B, HASWELL_B_GT3)
-CHIPSET(0x040E, HASWELL_E_GT1)
-CHIPSET(0x041E, HASWELL_E_GT2)
-CHIPSET(0x042E, HASWELL_E_GT3)
-CHIPSET(0x0C02, HASWELL_SDV_GT1)
-CHIPSET(0x0C12, HASWELL_SDV_GT2)
-CHIPSET(0x0C22, HASWELL_SDV_GT3)
-CHIPSET(0x0C06, HASWELL_SDV_M_GT1)
-CHIPSET(0x0C16, HASWELL_SDV_M_GT2)
-CHIPSET(0x0C26, HASWELL_SDV_M_GT3)
-CHIPSET(0x0C0A, HASWELL_SDV_S_GT1)
-CHIPSET(0x0C1A, HASWELL_SDV_S_GT2)
-CHIPSET(0x0C2A, HASWELL_SDV_S_GT3)
-CHIPSET(0x0C0B, HASWELL_SDV_B_GT1)
-CHIPSET(0x0C1B, HASWELL_SDV_B_GT2)
-CHIPSET(0x0C2B, HASWELL_SDV_B_GT3)
-CHIPSET(0x0C0E, HASWELL_SDV_E_GT1)
-CHIPSET(0x0C1E, HASWELL_SDV_E_GT2)
-CHIPSET(0x0C2E, HASWELL_SDV_E_GT3)
-CHIPSET(0x0A02, HASWELL_ULT_GT1)
-CHIPSET(0x0A12, HASWELL_ULT_GT2)
-CHIPSET(0x0A22, HASWELL_ULT_GT3)
-CHIPSET(0x0A06, HASWELL_ULT_M_GT1)
-CHIPSET(0x0A16, HASWELL_ULT_M_GT2)
-CHIPSET(0x0A26, HASWELL_ULT_M_GT3)
-CHIPSET(0x0A0A, HASWELL_ULT_S_GT1)
-CHIPSET(0x0A1A, HASWELL_ULT_S_GT2)
-CHIPSET(0x0A2A, HASWELL_ULT_S_GT3)
-CHIPSET(0x0A0B, HASWELL_ULT_B_GT1)
-CHIPSET(0x0A1B, HASWELL_ULT_B_GT2)
-CHIPSET(0x0A2B, HASWELL_ULT_B_GT3)
-CHIPSET(0x0A0E, HASWELL_ULT_E_GT1)
-CHIPSET(0x0A1E, HASWELL_ULT_E_GT2)
-CHIPSET(0x0A2E, HASWELL_ULT_E_GT3)
-CHIPSET(0x0D02, HASWELL_CRW_GT1)
-CHIPSET(0x0D12, HASWELL_CRW_GT2)
-CHIPSET(0x0D22, HASWELL_CRW_GT3)
-CHIPSET(0x0D06, HASWELL_CRW_M_GT1)
-CHIPSET(0x0D16, HASWELL_CRW_M_GT2)
-CHIPSET(0x0D26, HASWELL_CRW_M_GT3)
-CHIPSET(0x0D0A, HASWELL_CRW_S_GT1)
-CHIPSET(0x0D1A, HASWELL_CRW_S_GT2)
-CHIPSET(0x0D2A, HASWELL_CRW_S_GT3)
-CHIPSET(0x0D0B, HASWELL_CRW_B_GT1)
-CHIPSET(0x0D1B, HASWELL_CRW_B_GT2)
-CHIPSET(0x0D2B, HASWELL_CRW_B_GT3)
-CHIPSET(0x0D0E, HASWELL_CRW_E_GT1)
-CHIPSET(0x0D1E, HASWELL_CRW_E_GT2)
-CHIPSET(0x0D2E, HASWELL_CRW_E_GT3)
-CHIPSET(0x0F31, BAYTRAIL_M_1)
-CHIPSET(0x0F32, BAYTRAIL_M_2)
-CHIPSET(0x0F33, BAYTRAIL_M_3)
-CHIPSET(0x0157, BAYTRAIL_M_4)
-CHIPSET(0x0155, BAYTRAIL_D)
+CHIPSET(0x29A2, I965_G,                 "Intel(R) 965G")
+CHIPSET(0x2992, I965_Q,                 "Intel(R) 965Q")
+CHIPSET(0x2982, I965_G_1,               "Intel(R) 965G")
+CHIPSET(0x2972, I946_GZ,                "Intel(R) 946GZ")
+CHIPSET(0x2A02, I965_GM,                "Intel(R) 965GM")
+CHIPSET(0x2A12, I965_GME,               "Intel(R) 965GME/GLE")
+CHIPSET(0x2A42, GM45_GM,                "Mobile Intel® GM45 Express Chipset")
+CHIPSET(0x2E02, IGD_E_G,                "Intel(R) Integrated Graphics Device")
+CHIPSET(0x2E12, Q45_G,                  "Intel(R) Q45/Q43")
+CHIPSET(0x2E22, G45_G,                  "Intel(R) G45/G43")
+CHIPSET(0x2E32, G41_G,                  "Intel(R) G41")
+CHIPSET(0x2E42, B43_G,                  "Intel(R) B43")
+CHIPSET(0x2E92, B43_G1,                 "Intel(R) B43")
+CHIPSET(0x0042, ILD_G,                  "Intel(R) Ironlake Desktop")
+CHIPSET(0x0046, ILM_G,                  "Intel(R) Ironlake Mobile")
+CHIPSET(0x0102, SANDYBRIDGE_GT1,        "Intel(R) Sandybridge Desktop")
+CHIPSET(0x0112, SANDYBRIDGE_GT2,        "Intel(R) Sandybridge Desktop")
+CHIPSET(0x0122, SANDYBRIDGE_GT2_PLUS,   "Intel(R) Sandybridge Desktop")
+CHIPSET(0x0106, SANDYBRIDGE_M_GT1,      "Intel(R) Sandybridge Mobile")
+CHIPSET(0x0116, SANDYBRIDGE_M_GT2,      "Intel(R) Sandybridge Mobile")
+CHIPSET(0x0126, SANDYBRIDGE_M_GT2_PLUS, "Intel(R) Sandybridge Mobile")
+CHIPSET(0x010A, SANDYBRIDGE_S,          "Intel(R) Sandybridge Server")
+CHIPSET(0x0152, IVYBRIDGE_GT1,          "Intel(R) Ivybridge Desktop")
+CHIPSET(0x0162, IVYBRIDGE_GT2,          "Intel(R) Ivybridge Desktop")
+CHIPSET(0x0156, IVYBRIDGE_M_GT1,        "Intel(R) Ivybridge Mobile")
+CHIPSET(0x0166, IVYBRIDGE_M_GT2,        "Intel(R) Ivybridge Mobile")
+CHIPSET(0x015a, IVYBRIDGE_S_GT1,        "Intel(R) Ivybridge Server")
+CHIPSET(0x016a, IVYBRIDGE_S_GT2,        "Intel(R) Ivybridge Server")
+CHIPSET(0x0402, HASWELL_GT1,            "Intel(R) Haswell Desktop")
+CHIPSET(0x0412, HASWELL_GT2,            "Intel(R) Haswell Desktop")
+CHIPSET(0x0422, HASWELL_GT3,            "Intel(R) Haswell Desktop")
+CHIPSET(0x0406, HASWELL_M_GT1,          "Intel(R) Haswell Mobile")
+CHIPSET(0x0416, HASWELL_M_GT2,          "Intel(R) Haswell Mobile")
+CHIPSET(0x0426, HASWELL_M_GT3,          "Intel(R) Haswell Mobile")
+CHIPSET(0x040A, HASWELL_S_GT1,          "Intel(R) Haswell Server")
+CHIPSET(0x041A, HASWELL_S_GT2,          "Intel(R) Haswell Server")
+CHIPSET(0x042A, HASWELL_S_GT3,          "Intel(R) Haswell Server")
+CHIPSET(0x040B, HASWELL_B_GT1,          "Intel(R) Haswell")
+CHIPSET(0x041B, HASWELL_B_GT2,          "Intel(R) Haswell")
+CHIPSET(0x042B, HASWELL_B_GT3,          "Intel(R) Haswell")
+CHIPSET(0x040E, HASWELL_E_GT1,          "Intel(R) Haswell")
+CHIPSET(0x041E, HASWELL_E_GT2,          "Intel(R) Haswell")
+CHIPSET(0x042E, HASWELL_E_GT3,          "Intel(R) Haswell")
+CHIPSET(0x0C02, HASWELL_SDV_GT1,        "Intel(R) Haswell Desktop")
+CHIPSET(0x0C12, HASWELL_SDV_GT2,        "Intel(R) Haswell Desktop")
+CHIPSET(0x0C22, HASWELL_SDV_GT3,        "Intel(R) Haswell Desktop")
+CHIPSET(0x0C06, HASWELL_SDV_M_GT1,      "Intel(R) Haswell Mobile")
+CHIPSET(0x0C16, HASWELL_SDV_M_GT2,      "Intel(R) Haswell Mobile")
+CHIPSET(0x0C26, HASWELL_SDV_M_GT3,      "Intel(R) Haswell Mobile")
+CHIPSET(0x0C0A, HASWELL_SDV_S_GT1,      "Intel(R) Haswell Server")
+CHIPSET(0x0C1A, HASWELL_SDV_S_GT2,      "Intel(R) Haswell Server")
+CHIPSET(0x0C2A, HASWELL_SDV_S_GT3,      "Intel(R) Haswell Server")
+CHIPSET(0x0C0B, HASWELL_SDV_B_GT1,      "Intel(R) Haswell")
+CHIPSET(0x0C1B, HASWELL_SDV_B_GT2,      "Intel(R) Haswell")
+CHIPSET(0x0C2B, HASWELL_SDV_B_GT3,      "Intel(R) Haswell")
+CHIPSET(0x0C0E, HASWELL_SDV_E_GT1,      "Intel(R) Haswell")
+CHIPSET(0x0C1E, HASWELL_SDV_E_GT2,      "Intel(R) Haswell")
+CHIPSET(0x0C2E, HASWELL_SDV_E_GT3,      "Intel(R) Haswell")
+CHIPSET(0x0A02, HASWELL_ULT_GT1,        "Intel(R) Haswell Desktop")
+CHIPSET(0x0A12, HASWELL_ULT_GT2,        "Intel(R) Haswell Desktop")
+CHIPSET(0x0A22, HASWELL_ULT_GT3,        "Intel(R) Haswell Desktop")
+CHIPSET(0x0A06, HASWELL_ULT_M_GT1,      "Intel(R) Haswell Mobile")
+CHIPSET(0x0A16, HASWELL_ULT_M_GT2,      "Intel(R) Haswell Mobile")
+CHIPSET(0x0A26, HASWELL_ULT_M_GT3,      "Intel(R) Haswell Mobile")
+CHIPSET(0x0A0A, HASWELL_ULT_S_GT1,      "Intel(R) Haswell Server")
+CHIPSET(0x0A1A, HASWELL_ULT_S_GT2,      "Intel(R) Haswell Server")
+CHIPSET(0x0A2A, HASWELL_ULT_S_GT3,      "Intel(R) Haswell Server")
+CHIPSET(0x0A0B, HASWELL_ULT_B_GT1,      "Intel(R) Haswell")
+CHIPSET(0x0A1B, HASWELL_ULT_B_GT2,      "Intel(R) Haswell")
+CHIPSET(0x0A2B, HASWELL_ULT_B_GT3,      "Intel(R) Haswell")
+CHIPSET(0x0A0E, HASWELL_ULT_E_GT1,      "Intel(R) Haswell")
+CHIPSET(0x0A1E, HASWELL_ULT_E_GT2,      "Intel(R) Haswell")
+CHIPSET(0x0A2E, HASWELL_ULT_E_GT3,      "Intel(R) Haswell")
+CHIPSET(0x0D02, HASWELL_CRW_GT1,        "Intel(R) Haswell Desktop")
+CHIPSET(0x0D12, HASWELL_CRW_GT2,        "Intel(R) Haswell Desktop")
+CHIPSET(0x0D22, HASWELL_CRW_GT3,        "Intel(R) Haswell Desktop")
+CHIPSET(0x0D06, HASWELL_CRW_M_GT1,      "Intel(R) Haswell Mobile")
+CHIPSET(0x0D16, HASWELL_CRW_M_GT2,      "Intel(R) Haswell Mobile")
+CHIPSET(0x0D26, HASWELL_CRW_M_GT3,      "Intel(R) Haswell Mobile")
+CHIPSET(0x0D0A, HASWELL_CRW_S_GT1,      "Intel(R) Haswell Server")
+CHIPSET(0x0D1A, HASWELL_CRW_S_GT2,      "Intel(R) Haswell Server")
+CHIPSET(0x0D2A, HASWELL_CRW_S_GT3,      "Intel(R) Haswell")
+CHIPSET(0x0D0B, HASWELL_CRW_B_GT1,      "Intel(R) Haswell")
+CHIPSET(0x0D1B, HASWELL_CRW_B_GT2,      "Intel(R) Haswell")
+CHIPSET(0x0D2B, HASWELL_CRW_B_GT3,      "Intel(R) Haswell")
+CHIPSET(0x0D0E, HASWELL_CRW_E_GT1,      "Intel(R) Haswell")
+CHIPSET(0x0D1E, HASWELL_CRW_E_GT2,      "Intel(R) Haswell")
+CHIPSET(0x0D2E, HASWELL_CRW_E_GT3,      "Intel(R) Haswell")
+CHIPSET(0x0F31, BAYTRAIL_M_1,           "Intel(R) Bay Trail")
+CHIPSET(0x0F32, BAYTRAIL_M_2,           "Intel(R) Bay Trail")
+CHIPSET(0x0F33, BAYTRAIL_M_3,           "Intel(R) Bay Trail")
+CHIPSET(0x0157, BAYTRAIL_M_4,           "Intel(R) Bay Trail")
+CHIPSET(0x0155, BAYTRAIL_D,             "Intel(R) Bay Trail")
diff --git a/include/pci_ids/pci_id_driver_map.h b/include/pci_ids/pci_id_driver_map.h
index 41bb628f4c6..1d1f3c38bcd 100644
--- a/include/pci_ids/pci_id_driver_map.h
+++ b/include/pci_ids/pci_id_driver_map.h
@@ -8,13 +8,13 @@
 #endif
 
 static const int i915_chip_ids[] = {
-#define CHIPSET(chip, desc) chip,
+#define CHIPSET(chip, desc, name) chip,
 #include "pci_ids/i915_pci_ids.h"
 #undef CHIPSET
 };
 
 static const int i965_chip_ids[] = {
-#define CHIPSET(chip, desc) chip,
+#define CHIPSET(chip, desc, name) chip,
 #include "pci_ids/i965_pci_ids.h"
 #undef CHIPSET
 };