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| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2018-10-03 23:06:34 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2018-10-12 08:42:08 +0200 |
| commit | 416013b4f5caef69f8be15aaebf31d789b93f30f (patch) | |
| tree | 3fc44a7799518577ba2bf9f94ded0cf42a75b531 /common.py | |
| parent | 4b74f05f6b635a8359d1e4a59c8d0cd69d1d9e30 (diff) | |
radv: emit the GLC bit for SSBO loads/stores when needed
This fixes some new memory model tests:
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.*
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108112
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Diffstat (limited to 'common.py')
0 files changed, 0 insertions, 0 deletions