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authorIan Romanick <ian.d.romanick@intel.com>2016-10-24 20:24:56 -0700
committerIan Romanick <ian.d.romanick@intel.com>2017-01-20 15:41:23 -0800
commitfc16bf125f9428b57526a216e5097e31c94b7623 (patch)
treec1fdf83515484d4b138deee18ca47541aac2fda0
parent51807c6493ac6edf76951cfe648235a92486778d (diff)
i965: Split SIMD16 CMP of Q and UQ instructions
This is basically the same as happens for doubles. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_nir.cpp43
1 files changed, 29 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 17d94565ee5..c6c91ebf23c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -960,25 +960,40 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
case nir_op_ilt:
case nir_op_ult:
- assert(nir_dest_bit_size(instr->dest.dest) < 64);
- bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_L);
- break;
-
case nir_op_ige:
case nir_op_uge:
- assert(nir_dest_bit_size(instr->dest.dest) < 64);
- bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_GE);
- break;
-
case nir_op_ieq:
- assert(nir_dest_bit_size(instr->dest.dest) < 64);
- bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_Z);
- break;
+ case nir_op_ine: {
+ fs_reg dest = result;
+ if (nir_src_bit_size(instr->src[0].src) > 32) {
+ dest = bld.vgrf(BRW_REGISTER_TYPE_UQ, 1);
+ }
- case nir_op_ine:
- assert(nir_dest_bit_size(instr->dest.dest) < 64);
- bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_NZ);
+ brw_conditional_mod cond;
+ switch (instr->op) {
+ case nir_op_ilt:
+ case nir_op_ult:
+ cond = BRW_CONDITIONAL_L;
+ break;
+ case nir_op_ige:
+ case nir_op_uge:
+ cond = BRW_CONDITIONAL_GE;
+ break;
+ case nir_op_ieq:
+ cond = BRW_CONDITIONAL_Z;
+ break;
+ case nir_op_ine:
+ cond = BRW_CONDITIONAL_NZ;
+ break;
+ default:
+ unreachable("bad opcode");
+ }
+ bld.CMP(dest, op[0], op[1], cond);
+ if (nir_src_bit_size(instr->src[0].src) > 32) {
+ bld.MOV(result, subscript(dest, BRW_REGISTER_TYPE_UD, 0));
+ }
break;
+ }
case nir_op_inot:
if (devinfo->gen >= 8) {