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authorIan Romanick <ian.d.romanick@intel.com>2016-09-01 12:00:10 -0700
committerIan Romanick <ian.d.romanick@intel.com>2017-01-20 15:41:23 -0800
commitf2fa5105946a014f1013b288db37d17b2c19930a (patch)
tree1c7dd62969109c2d5a552bc5501fae37ed39d461
parent409e0b2d48fea4afa9ddfcd171ee33dbd3ace2f1 (diff)
i965: Enable emitting Q and UQ instructions in the fs backend
v2: Fixup assertion in brw_reg_type_to_hw_type to allow BRW_REGISTER_TYPE_{UQ,Q} on Gen8+. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c5
-rw-r--r--src/mesa/drivers/dri/i965/brw_inst.h8
2 files changed, 12 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 8d08d1856ab..4b557d98b48 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -144,7 +144,7 @@ brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
assert(type < ARRAY_SIZE(hw_types));
assert(hw_types[type] != -1);
assert(devinfo->gen >= 7 || type < BRW_REGISTER_TYPE_DF);
- assert(devinfo->gen >= 8 || type < BRW_REGISTER_TYPE_HF);
+ assert(devinfo->gen >= 8 || type < BRW_REGISTER_TYPE_Q);
return hw_types[type];
}
}
@@ -411,6 +411,9 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
if (reg.type == BRW_REGISTER_TYPE_DF ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM)
brw_inst_set_imm_df(devinfo, inst, reg.df);
+ else if (reg.type == BRW_REGISTER_TYPE_UQ ||
+ reg.type == BRW_REGISTER_TYPE_Q)
+ brw_inst_set_imm_uq(devinfo, inst, reg.u64);
else
brw_inst_set_imm_ud(devinfo, inst, reg.ud);
diff --git a/src/mesa/drivers/dri/i965/brw_inst.h b/src/mesa/drivers/dri/i965/brw_inst.h
index d98bbf538a8..13fce97e539 100644
--- a/src/mesa/drivers/dri/i965/brw_inst.h
+++ b/src/mesa/drivers/dri/i965/brw_inst.h
@@ -627,6 +627,14 @@ brw_inst_set_imm_df(const struct gen_device_info *devinfo,
brw_inst_set_bits(insn, 127, 64, dt.u);
}
+static inline void
+brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
+ brw_inst *insn, uint64_t value)
+{
+ (void) devinfo;
+ brw_inst_set_bits(insn, 127, 64, value);
+}
+
/** @} */
/* The AddrImm fields are split into two discontiguous sections on Gen8+ */