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authorLeo Liu <leo.liu@amd.com>2017-08-21 11:50:38 -0400
committerLeo Liu <leo.liu@amd.com>2017-08-22 15:12:19 -0400
commitdf6c087a383f801c32352309e9b858340989955d (patch)
tree527e3c8975600e1fa9beec8ee41c7ac65ae4c1ac
parente29ccaac298d04ad4272af2d8b8d7a953c523e28 (diff)
radeon/vcn: correct target buffer pitch calculation
since the way should be as same as UVD Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian K├Ânig <christian.koenig@amd.com>
-rw-r--r--src/gallium/drivers/radeon/radeon_vcn_dec.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index a60b969a273..51391627d5f 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -631,7 +631,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->db_pitch = align(dec->base.width, 32);
decode->db_surf_tile_config = 0;
- decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.bpe;;
+ decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
decode->dt_uv_pitch = decode->dt_pitch / 2;
decode->dt_tiling_mode = 0;