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authorXiang, Haihao <haihao.xiang@intel.com>2008-02-19 15:59:50 +0800
committerXiang, Haihao <haihao.xiang@intel.com>2008-02-19 15:59:50 +0800
commitda476ff02dd357d9909a2df9891ee645f5f776a0 (patch)
tree5a7cb46595c675749a240aefe77361c8790274bb
parent77e3b5d28ba47f1910b9db0b1e0e36e951365d1e (diff)
i965: new integrated graphics chipset support
-rw-r--r--src/mesa/drivers/dri/i965/brw_aub_playback.c7
-rw-r--r--src/mesa/drivers/dri/i965/brw_clip.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_clip_state.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_clip_util.c14
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h12
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu.c3
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu.h3
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c31
-rw-r--r--src/mesa/drivers/dri/i965/brw_gs.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c33
-rw-r--r--src/mesa/drivers/dri/i965/brw_sf.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_sf_state.c3
-rw-r--r--src/mesa/drivers/dri/i965/brw_state.h1
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_batch.c1
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_structs.h105
-rw-r--r--src/mesa/drivers/dri/i965/brw_urb.c8
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs_emit.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm.c3
-rw-r--r--src/mesa/drivers/dri/i965/intel_context.c3
-rw-r--r--src/mesa/drivers/dri/i965/intel_context.h2
22 files changed, 185 insertions, 60 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_aub_playback.c b/src/mesa/drivers/dri/i965/brw_aub_playback.c
index 2433d50c116..99d9475510e 100644
--- a/src/mesa/drivers/dri/i965/brw_aub_playback.c
+++ b/src/mesa/drivers/dri/i965/brw_aub_playback.c
@@ -143,13 +143,15 @@ static struct {
{ CMD_CONST_BUFFER, "CONST_BUFFER", 1 },
{ CMD_STATE_BASE_ADDRESS, "STATE_BASE_ADDRESS", 1 },
{ CMD_STATE_INSN_POINTER, "STATE_INSN_POINTER", 1 },
- { CMD_PIPELINE_SELECT, "PIPELINE_SELECT", 0, },
+ { CMD_PIPELINE_SELECT_965, "PIPELINE_SELECT", 0, },
+ { CMD_PIPELINE_SELECT_IGD, "PIPELINE_SELECT", 0,},
{ CMD_PIPELINED_STATE_POINTERS, "PIPELINED_STATE_POINTERS", 1 },
{ CMD_BINDING_TABLE_PTRS, "BINDING_TABLE_PTRS", 1 },
{ CMD_VERTEX_BUFFER, "VERTEX_BUFFER", 1 },
{ CMD_VERTEX_ELEMENT, "VERTEX_ELEMENT", 1 },
{ CMD_INDEX_BUFFER, "INDEX_BUFFER", 1 },
- { CMD_VF_STATISTICS, "VF_STATISTICS", 0 },
+ { CMD_VF_STATISTICS_965, "VF_STATISTICS", 0 },
+ { CMD_VF_STATISTICS_IGD, "VF_STATISTICS", 0 },
{ CMD_DRAW_RECT, "DRAW_RECT", 1 },
{ CMD_BLEND_CONSTANT_COLOR, "BLEND_CONSTANT_COLOR", 1 },
{ CMD_CHROMA_KEY, "CHROMA_KEY", 1 },
@@ -157,6 +159,7 @@ static struct {
{ CMD_POLY_STIPPLE_OFFSET, "POLY_STIPPLE_OFFSET", 1 },
{ CMD_POLY_STIPPLE_PATTERN, "POLY_STIPPLE_PATTERN", 1 },
{ CMD_LINE_STIPPLE_PATTERN, "LINE_STIPPLE_PATTERN", 1 },
+ { CMD_AA_LINE_PARAMETERS, "AA_LINE_PARAMETERS", 1},
{ CMD_GLOBAL_DEPTH_OFFSET_CLAMP, "GLOBAL_DEPTH_OFFSET_CLAMP", 1 },
{ CMD_PIPE_CONTROL, "PIPE_CONTROL", 1 },
{ CMD_MI_FLUSH, "MI_FLUSH", 0 },
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
index 8287fd9edf3..8f907bea7bd 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -60,7 +60,7 @@ static void compile_clip_prog( struct brw_context *brw,
/* Begin the compilation:
*/
- brw_init_compile(&c.func);
+ brw_init_compile(brw, &c.func);
c.func.single_program_flow = 1;
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 1e6d6fa1762..37a25a98fe3 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -72,6 +72,10 @@ static void upload_clip_unit( struct brw_context *brw )
clip.clip5.viewport_xy_clip_enable = 1;
clip.clip5.vertex_position_space = BRW_CLIP_NDCSPACE;
clip.clip5.api_mode = BRW_CLIP_API_OGL;
+
+ if (BRW_IS_IGD(brw))
+ clip.clip5.negative_w_clip_test = 1;
+
clip.clip6.clipper_viewport_state_ptr = 0;
clip.viewport_xmin = -1;
clip.viewport_xmax = 1;
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c
index e61f55c9f3f..fc484a73936 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -343,12 +343,14 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c )
release_tmp(c, tmp);
}
- /* Test for -ve rhw workaround
- */
- brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
- brw_AND(p, vec1(brw_null_reg()), incoming, brw_imm_ud(1<<20));
- brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+ if (BRW_IS_IGD(p->brw)) {
+ /* Test for -ve rhw workaround
+ */
+ brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
+ brw_AND(p, vec1(brw_null_reg()), incoming, brw_imm_ud(1<<20));
+ brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
+ }
+ brw_set_predicate_control(p, BRW_PREDICATE_NONE);
}
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e8f878a7018..101828b8ce6 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -815,14 +815,16 @@
#define CMD_STATE_BASE_ADDRESS 0x6101
#define CMD_STATE_INSN_POINTER 0x6102
-#define CMD_PIPELINE_SELECT 0x6104
+#define CMD_PIPELINE_SELECT_965 0x6104
+#define CMD_PIPELINE_SELECT_IGD 0x6904
#define CMD_PIPELINED_STATE_POINTERS 0x7800
#define CMD_BINDING_TABLE_PTRS 0x7801
#define CMD_VERTEX_BUFFER 0x7808
#define CMD_VERTEX_ELEMENT 0x7809
#define CMD_INDEX_BUFFER 0x780a
-#define CMD_VF_STATISTICS 0x780b
+#define CMD_VF_STATISTICS_965 0x780b
+#define CMD_VF_STATISTICS_IGD 0x680b
#define CMD_DRAW_RECT 0x7900
#define CMD_BLEND_CONSTANT_COLOR 0x7901
@@ -832,6 +834,7 @@
#define CMD_POLY_STIPPLE_PATTERN 0x7907
#define CMD_LINE_STIPPLE_PATTERN 0x7908
#define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7909
+#define CMD_AA_LINE_PARAMETERS 0x790a
#define CMD_PIPE_CONTROL 0x7a00
@@ -845,6 +848,9 @@
#define R02_PRIM_END 0x1
#define R02_PRIM_START 0x2
-
+#define BRW_IS_IGD(brw) ((brw)->intel.intelScreen->deviceID == PCI_CHIP_IGD_GM)
+#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_IGD(brw)) ? CMD_PIPELINE_SELECT_IGD : CMD_PIPELINE_SELECT_965)
+#define CMD_VF_STATISTICS(brw) ((BRW_IS_IGD(brw)) ? CMD_VF_STATISTICS_IGD : CMD_VF_STATISTICS_965)
+#define URB_SIZES(brw) ((BRW_IS_IGD(brw)) ? 384 : 256) /* 512 bit unit */
#endif
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index d1244befd78..b3ae4eef334 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -101,8 +101,9 @@ void brw_pop_insn_state( struct brw_compile *p )
/***********************************************************************
*/
-void brw_init_compile( struct brw_compile *p )
+void brw_init_compile( struct brw_context *brw, struct brw_compile *p )
{
+ p->brw = brw;
p->nr_insn = 0;
p->current = p->stack;
memset(p->current, 0, sizeof(p->current[0]));
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 52f89d577ca..9d46aac264f 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -105,6 +105,7 @@ struct brw_compile {
GLuint flag_value;
GLboolean single_program_flow;
+ struct brw_context *brw;
};
@@ -680,7 +681,7 @@ void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value )
void brw_set_predicate_control( struct brw_compile *p, GLuint pc );
void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional );
-void brw_init_compile( struct brw_compile *p );
+void brw_init_compile( struct brw_context *, struct brw_compile *p );
const GLuint *brw_get_program( struct brw_compile *p, GLuint *sz );
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 9992b47d8ae..1c717e418a8 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -318,7 +318,8 @@ static void brw_set_dp_read_message( struct brw_instruction *insn,
insn->bits3.dp_read.end_of_thread = end_of_thread;
}
-static void brw_set_sampler_message( struct brw_instruction *insn,
+static void brw_set_sampler_message(struct brw_context *brw,
+ struct brw_instruction *insn,
GLuint binding_table_index,
GLuint sampler,
GLuint msg_type,
@@ -328,14 +329,24 @@ static void brw_set_sampler_message( struct brw_instruction *insn,
{
brw_set_src1(insn, brw_imm_d(0));
- insn->bits3.sampler.binding_table_index = binding_table_index;
- insn->bits3.sampler.sampler = sampler;
- insn->bits3.sampler.msg_type = msg_type;
- insn->bits3.sampler.return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
- insn->bits3.sampler.response_length = response_length;
- insn->bits3.sampler.msg_length = msg_length;
- insn->bits3.sampler.end_of_thread = eot;
- insn->bits3.sampler.msg_target = BRW_MESSAGE_TARGET_SAMPLER;
+ if (BRW_IS_IGD(brw)) {
+ insn->bits3.sampler_igd.binding_table_index = binding_table_index;
+ insn->bits3.sampler_igd.sampler = sampler;
+ insn->bits3.sampler_igd.msg_type = msg_type;
+ insn->bits3.sampler_igd.response_length = response_length;
+ insn->bits3.sampler_igd.msg_length = msg_length;
+ insn->bits3.sampler_igd.end_of_thread = eot;
+ insn->bits3.sampler_igd.msg_target = BRW_MESSAGE_TARGET_SAMPLER;
+ } else {
+ insn->bits3.sampler.binding_table_index = binding_table_index;
+ insn->bits3.sampler.sampler = sampler;
+ insn->bits3.sampler.msg_type = msg_type;
+ insn->bits3.sampler.return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
+ insn->bits3.sampler.response_length = response_length;
+ insn->bits3.sampler.msg_length = msg_length;
+ insn->bits3.sampler.end_of_thread = eot;
+ insn->bits3.sampler.msg_target = BRW_MESSAGE_TARGET_SAMPLER;
+ }
}
@@ -985,7 +996,7 @@ void brw_SAMPLE(struct brw_compile *p,
brw_set_dest(insn, dest);
brw_set_src0(insn, src0);
- brw_set_sampler_message(insn,
+ brw_set_sampler_message(p->brw, insn,
binding_table_index,
sampler,
msg_type,
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 73263a5fff4..119d07d4f9b 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -65,7 +65,7 @@ static void compile_gs_prog( struct brw_context *brw,
/* Begin the compilation:
*/
- brw_init_compile(&c.func);
+ brw_init_compile(brw, &c.func);
c.func.single_program_flow = 1;
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index d5779680ffc..fe476c95cf6 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -249,7 +249,7 @@ static void upload_depthbuffer(struct brw_context *brw)
memset(&bd, 0, sizeof(bd));
bd.header.bits.opcode = CMD_DEPTH_BUFFER;
- bd.header.bits.length = sizeof(bd)/4-2;
+ bd.header.bits.length = BRW_IS_IGD(brw) ? (sizeof(bd)/4-2) : (sizeof(bd)/4-3);
bd.dword1.bits.pitch = (region->pitch * region->cpp) - 1;
switch (region->cpp) {
@@ -359,6 +359,33 @@ const struct brw_tracked_state brw_polygon_stipple_offset = {
.update = upload_polygon_stipple_offset
};
+/**********************************************************************
+ * AA Line parameters
+ */
+static void upload_aa_line_parameters(struct brw_context *brw)
+{
+ struct brw_aa_line_parameters balp;
+
+ if (!BRW_IS_IGD(brw))
+ return;
+
+ /* use legacy aa line coverage computation */
+ memset(&balp, 0, sizeof(balp));
+ balp.header.opcode = CMD_AA_LINE_PARAMETERS;
+ balp.header.length = sizeof(balp) / 4 - 2;
+
+ BRW_CACHED_BATCH_STRUCT(brw, &balp);
+}
+
+const struct brw_tracked_state brw_aa_line_parameters = {
+ .dirty = {
+ .mesa = 0,
+ .brw = BRW_NEW_CONTEXT,
+ .cache = 0
+ },
+ .update = upload_aa_line_parameters
+};
+
/***********************************************************************
* Line stipple packet
*/
@@ -441,7 +468,7 @@ static void upload_invarient_state( struct brw_context *brw )
struct brw_pipeline_select ps;
memset(&ps, 0, sizeof(ps));
- ps.header.opcode = CMD_PIPELINE_SELECT;
+ ps.header.opcode = CMD_PIPELINE_SELECT(brw);
ps.header.pipeline_select = 0;
BRW_BATCH_STRUCT(brw, &ps);
}
@@ -477,7 +504,7 @@ static void upload_invarient_state( struct brw_context *brw )
struct brw_vf_statistics vfs;
memset(&vfs, 0, sizeof(vfs));
- vfs.opcode = CMD_VF_STATISTICS;
+ vfs.opcode = CMD_VF_STATISTICS(brw);
if (INTEL_DEBUG & DEBUG_STATS)
vfs.statistics_enable = 1;
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index df18a487998..6dcfa628620 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -57,7 +57,7 @@ static void compile_sf_prog( struct brw_context *brw,
/* Begin the compilation:
*/
- brw_init_compile(&c.func);
+ brw_init_compile(brw, &c.func);
c.key = *key;
c.nr_attrs = brw_count_bits(c.key.attrs);
diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index bfac52d765b..2fd75a0c571 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -185,7 +185,8 @@ static void upload_sf_unit( struct brw_context *brw )
sf.sf6.point_rast_rule = 1; /* opengl conventions */
sf.sf7.point_size = brw->attribs.Point->_Size * (1<<3);
sf.sf7.use_point_size_state = !brw->attribs.Point->_Attenuated;
-
+ sf.sf7.aa_line_distance_mode = 0;
+
/* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
*/
sf.sf7.trifan_pv = 2;
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index b4cbdd7a380..41ac09514b2 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -50,6 +50,7 @@ const struct brw_tracked_state brw_gs_prog;
const struct brw_tracked_state brw_gs_unit;
const struct brw_tracked_state brw_drawing_rect;
const struct brw_tracked_state brw_line_stipple;
+const struct brw_tracked_state brw_aa_line_parameters;
const struct brw_tracked_state brw_pipelined_state_pointers;
const struct brw_tracked_state brw_binding_table_pointers;
const struct brw_tracked_state brw_depthbuffer;
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index 909b0acd121..c93d66a3a9e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -103,6 +103,7 @@ static void clear_batch_cache( struct brw_context *brw )
void brw_clear_batch_cache_flush( struct brw_context *brw )
{
+ bmFinishFenceLock(&(brw->intel), bmSetFenceLock(&(brw->intel)));
clear_batch_cache(brw);
brw->wrap = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 92c07c29624..9bd28817aa6 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -92,7 +92,7 @@ const struct brw_tracked_state *atoms[] =
&brw_polygon_stipple_offset,
&brw_line_stipple,
-
+ &brw_aa_line_parameters,
/* Ordering of the commands below is documented as fixed.
*/
#if 0
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 10fee944e8d..a799122cb77 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -141,7 +141,8 @@ struct brw_depthbuffer
struct {
GLuint pitch:18;
GLuint format:3;
- GLuint pad:4;
+ GLuint pad:2;
+ GLuint software_tiled_rendering_mode:2;
GLuint depth_offset_disable:1;
GLuint tile_walk:1;
GLuint tiled_surface:1;
@@ -166,12 +167,20 @@ struct brw_depthbuffer
union {
struct {
- GLuint pad:12;
- GLuint min_array_element:9;
+ GLuint pad:10;
+ GLuint min_array_element:11;
GLuint depth:11;
} bits;
GLuint dword;
} dword4;
+
+ union {
+ struct {
+ GLuint xoffset:16;
+ GLuint yoffset:16;
+ } bits;
+ GLuint dword;
+ } dword5; /* NEW in Integrated Graphics Device */
};
struct brw_drawrect
@@ -213,6 +222,25 @@ struct brw_indexbuffer
GLuint buffer_end;
};
+/* NEW in Integrated Graphics Device */
+struct brw_aa_line_parameters
+{
+ struct header header;
+
+ struct {
+ GLuint aa_coverage_scope:8;
+ GLuint pad0:8;
+ GLuint aa_coverage_bias:8;
+ GLuint pad1:8;
+ } bits0;
+
+ struct {
+ GLuint aa_coverage_endcap_slope:8;
+ GLuint pad0:8;
+ GLuint aa_coverage_endcap_bias:8;
+ GLuint pad1:8;
+ } bits1;
+};
struct brw_line_stipple
{
@@ -315,7 +343,8 @@ struct brw_pipe_control
{
GLuint length:8;
GLuint notify_enable:1;
- GLuint pad:2;
+ GLuint texture_cache_flush_enable:1;
+ GLuint indirect_state_pointers_disable:1;
GLuint instruction_state_cache_flush_enable:1;
GLuint write_cache_flush_enable:1;
GLuint depth_stall_enable:1;
@@ -547,8 +576,8 @@ struct brw_clip_unit_state
GLuint pad1:1;
GLuint urb_entry_allocation_size:5;
GLuint pad2:1;
- GLuint max_threads:1; /* may be less */
- GLuint pad3:6;
+ GLuint max_threads:5; /* may be less */
+ GLuint pad3:2;
} thread4;
struct
@@ -557,7 +586,7 @@ struct brw_clip_unit_state
GLuint clip_mode:3;
GLuint userclip_enable_flags:8;
GLuint userclip_must_clip:1;
- GLuint pad1:1;
+ GLuint negative_w_clip_test:1;
GLuint guard_band_enable:1;
GLuint viewport_z_clip_enable:1;
GLuint viewport_xy_clip_enable:1;
@@ -724,7 +753,8 @@ struct brw_sf_unit_state
GLuint use_point_size_state:1;
GLuint subpixel_precision:1;
GLuint sprite_point:1;
- GLuint pad0:11;
+ GLuint pad0:10;
+ GLuint aa_line_distance_mode:1;
GLuint trifan_pv:2;
GLuint linestrip_pv:2;
GLuint tristrip_pv:2;
@@ -749,8 +779,8 @@ struct brw_gs_unit_state
GLuint pad1:1;
GLuint urb_entry_allocation_size:5;
GLuint pad2:1;
- GLuint max_threads:1;
- GLuint pad3:6;
+ GLuint max_threads:5;
+ GLuint pad3:2;
} thread4;
struct
@@ -764,9 +794,14 @@ struct brw_gs_unit_state
struct
{
GLuint max_vp_index:4;
- GLuint pad0:26;
- GLuint reorder_enable:1;
+ GLuint pad0:12;
+ GLuint svbi_post_inc_value:10;
GLuint pad1:1;
+ GLuint svbi_post_inc_enable:1;
+ GLuint svbi_payload:1;
+ GLuint discard_adjaceny:1;
+ GLuint reorder_enable:1;
+ GLuint pad2:1;
} gs6;
};
@@ -786,8 +821,8 @@ struct brw_vs_unit_state
GLuint pad1:1;
GLuint urb_entry_allocation_size:5;
GLuint pad2:1;
- GLuint max_threads:4;
- GLuint pad3:3;
+ GLuint max_threads:6;
+ GLuint pad3:1;
} thread4;
struct
@@ -815,7 +850,7 @@ struct brw_wm_unit_state
struct {
GLuint stats_enable:1;
- GLuint pad0:1;
+ GLuint depth_buffer_clear:1;
GLuint sampler_count:3;
GLuint sampler_state_pointer:27;
} wm4;
@@ -825,7 +860,9 @@ struct brw_wm_unit_state
GLuint enable_8_pix:1;
GLuint enable_16_pix:1;
GLuint enable_32_pix:1;
- GLuint pad0:7;
+ GLuint enable_con_32_pix:1;
+ GLuint enable_con_64_pix:1;
+ GLuint pad0:5;
GLuint legacy_global_depth_bias:1;
GLuint line_stipple:1;
GLuint depth_offset:1;
@@ -838,9 +875,8 @@ struct brw_wm_unit_state
GLuint program_computes_depth:1;
GLuint program_uses_killpixel:1;
GLuint legacy_line_rast: 1;
- GLuint pad1:1;
- GLuint max_threads:6;
- GLuint pad2:1;
+ GLuint transposed_urb_read_enable:1;
+ GLuint max_threads:7;
} wm5;
GLfloat global_depth_offset_constant;
@@ -978,10 +1014,26 @@ struct brw_surface_state
} ss3;
struct {
- GLuint pad:19;
- GLuint min_array_elt:9;
+ GLuint multisample_position_palette_index:3;
+ GLuint pad1:1;
+ GLuint num_multisamples:3;
+ GLuint pad0:1;
+ GLuint render_target_view_extent:9;
+ GLuint min_array_elt:11;
GLuint min_lod:4;
} ss4;
+
+ struct {
+ GLuint pad1:16;
+ GLuint llc_mapping:1;
+ GLuint mlc_mapping:1;
+ GLuint gfdt:1;
+ GLuint gfdt_src:1;
+ GLuint y_offset:4;
+ GLuint pad0:1;
+ GLuint x_offset:7;
+ } ss5; /* NEW in Integrated Graphics Device */
+
};
@@ -1301,6 +1353,17 @@ struct brw_instruction
GLuint end_of_thread:1;
} sampler;
+ struct {
+ GLuint binding_table_index:8;
+ GLuint sampler:4;
+ GLuint msg_type:4;
+ GLuint response_length:4;
+ GLuint msg_length:4;
+ GLuint msg_target:4;
+ GLuint pad1:3;
+ GLuint end_of_thread:1;
+ } sampler_igd;
+
struct brw_urb_immediate urb;
struct {
diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c
index 64f5904ac68..4ca6e99db0b 100644
--- a/src/mesa/drivers/dri/i965/brw_urb.c
+++ b/src/mesa/drivers/dri/i965/brw_urb.c
@@ -69,7 +69,7 @@ static GLboolean check_urb_layout( struct brw_context *brw )
brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize;
brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize;
- return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= 256;
+ return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= URB_SIZES(brw);
}
/* Most minimal update, forces re-emit of URB fence packet after GS
@@ -153,7 +153,7 @@ static void recalculate_urb_fence( struct brw_context *brw )
brw->urb.clip_start,
brw->urb.sf_start,
brw->urb.cs_start,
- 256);
+ URB_SIZES(brw));
brw->state.dirty.brw |= BRW_NEW_URB_FENCE;
}
@@ -191,13 +191,13 @@ void brw_upload_urb_fence(struct brw_context *brw)
/* The ordering below is correct, not the layout in the
* instruction.
*
- * There are 256 urb reg pairs in total.
+ * There are 256/384 urb reg pairs in total.
*/
uf.bits0.vs_fence = brw->urb.gs_start;
uf.bits0.gs_fence = brw->urb.clip_start;
uf.bits0.clp_fence = brw->urb.sf_start;
uf.bits1.sf_fence = brw->urb.cs_start;
- uf.bits1.cs_fence = 256;
+ uf.bits1.cs_fence = URB_SIZES(brw);
BRW_BATCH_STRUCT(brw, &uf);
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index e173f6fce3e..50826d9062c 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -49,7 +49,7 @@ static void do_vs_prog( struct brw_context *brw,
memset(&c, 0, sizeof(c));
memcpy(&c.key, key, sizeof(*key));
- brw_init_compile(&c.func);
+ brw_init_compile(brw, &c.func);
c.vp = vp;
c.prog_data.outputs_written = vp->program.Base.OutputsWritten;
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 6eb11b19ad2..c38e998d48f 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -845,7 +845,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
* Later, clipping will detect ucp[6] and ensure the primitive is
* clipped against all fixed planes.
*/
- if (!c->key.know_w_is_one) {
+ if (!BRW_IS_IGD(p->brw) && !c->key.know_w_is_one) {
brw_CMP(p,
vec8(brw_null_reg()),
BRW_CONDITIONAL_L,
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 1497dc79687..f80ba178039 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -150,7 +150,6 @@ static void do_wm_prog( struct brw_context *brw,
c->fp = fp;
c->env_param = brw->intel.ctx.FragmentProgram.Parameters;
-
/* Augment fragment program. Add instructions for pre- and
* post-fragment-program tasks such as interpolation and fogging.
*/
@@ -175,7 +174,7 @@ static void do_wm_prog( struct brw_context *brw,
/* This is where we start emitting gen4 code:
*/
- brw_init_compile(&c->func);
+ brw_init_compile(brw, &c->func);
brw_wm_pass2(c);
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 33efed431db..5ee52829623 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -118,6 +118,9 @@ static const GLubyte *intelGetString( GLcontext *ctx, GLenum name )
case PCI_CHIP_I965_GM:
chipset = "Intel(R) 965GM"; break;
break;
+ case PCI_CHIP_IGD_GM:
+ chipset = "Intel(R) Integrated Graphics Device";
+ break;
default:
chipset = "Unknown Intel Chipset"; break;
}
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 9f69f23706d..a2447574cad 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -387,6 +387,8 @@ extern int INTEL_DEBUG;
#define PCI_CHIP_I946_GZ 0x2972
#define PCI_CHIP_I965_GM 0x2A02
+#define PCI_CHIP_IGD_GM 0x2A42
+
/* ================================================================
* intel_context.c: