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authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>2020-08-14 00:58:06 +0200
committerMarge Bot <eric+marge@anholt.net>2020-09-20 23:51:58 +0000
commitd78df70c2a85fd846d40b71b9e213122347bea1b (patch)
treef3127b4e33f0b68619109f9ff9056faa30d7a9cf
parentecc19e9819c021d5e10246492284d8f68b019315 (diff)
radv,radeonsi: Disable compression on interop depth images
If we want to use HTILE correctly we need to communicate extra stuff like clear colors. (Unlike DCC there is no HTILE FCE) CC: mesa-stable Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6617>
-rw-r--r--src/amd/vulkan/radv_image.c1
-rw-r--r--src/gallium/drivers/radeonsi/si_texture.c3
2 files changed, 3 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 43ccec304bb..cc0ae660268 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -268,6 +268,7 @@ radv_use_htile_for_image(const struct radv_device *device,
const struct radv_image *image)
{
return image->info.levels == 1 &&
+ !image->shareable &&
((image->info.width * image->info.height >= 8 * 8) ||
(device->instance->debug_flags & RADV_DEBUG_FORCE_COMPRESS));
}
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 448e7497be5..b66f8eba6d2 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -237,7 +237,8 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
if (!is_flushed_depth && is_depth) {
flags |= RADEON_SURF_ZBUFFER;
- if (sscreen->debug_flags & DBG(NO_HYPERZ)) {
+ if ((sscreen->debug_flags & DBG(NO_HYPERZ)) ||
+ (ptex->bind & PIPE_BIND_SHARED) || is_imported) {
flags |= RADEON_SURF_NO_HTILE;
} else if (tc_compatible_htile &&
(sscreen->info.chip_class >= GFX9 || array_mode == RADEON_SURF_MODE_2D)) {