diff options
| author | Mario Kleiner <mario.kleiner.de@gmail.com> | 2017-12-15 23:04:55 +0100 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2018-01-03 22:57:56 +0100 |
| commit | cfb98bcdd0ef14939247c5063f255e3f91bf8ce8 (patch) | |
| tree | c26d99ba7edf7c9efece8c59093d513254f4b21c | |
| parent | 67674ad0dc68eb128e5f176f772d902931deb1de (diff) | |
i965/screen: Honor 'allow_rgb10_configs' option. (v2)
Allows to prevent exposing RGB10 configs and visuals to
clients.
v2: Rename expose_rgb10_configs to allow_rgb10_configs,
as suggested by Emil.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_screen.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 746c568de27..3e016b5b7ae 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -2063,11 +2063,20 @@ intel_screen_make_configs(__DRIscreen *dri_screen) else num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */ + /* Shall we expose 10 bpc formats? */ + bool allow_rgb10_configs = driQueryOptionb(&dri_screen->optionCache, + "allow_rgb10_configs"); + /* Generate singlesample configs without accumulation buffer. */ for (unsigned i = 0; i < num_formats; i++) { __DRIconfig **new_configs; int num_depth_stencil_bits = 2; + if (!allow_rgb10_configs && + (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || + formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) + continue; + /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil * buffer that has a different number of bits per pixel than the color * buffer, gen >= 6 supports this. @@ -2104,6 +2113,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen) for (unsigned i = 0; i < num_formats; i++) { __DRIconfig **new_configs; + if (!allow_rgb10_configs && + (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || + formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) + continue; + if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { depth_bits[0] = 16; stencil_bits[0] = 0; @@ -2137,6 +2151,11 @@ intel_screen_make_configs(__DRIscreen *dri_screen) if (devinfo->gen < 6) break; + if (!allow_rgb10_configs && + (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || + formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) + continue; + __DRIconfig **new_configs; const int num_depth_stencil_bits = 2; int num_msaa_modes = 0; |