diff options
| author | Michel Dänzer <michel.daenzer@amd.com> | 2013-02-15 11:30:50 +0100 |
|---|---|---|
| committer | Michel Dänzer <michel@daenzer.net> | 2013-02-22 20:24:24 +0100 |
| commit | cb8bacd87a5b53421bd49cd6656d4dbc019414fa (patch) | |
| tree | 881faf35ab62ef20a3ccb734ffc6af1fd4dd8353 | |
| parent | 0d08abd461e99863b195d879d40c075f63b0d6b6 (diff) | |
radeonsi: Use stencil surface level information for stencil texturing
7 more little dwarves^W piglits.
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit 8356962853727136f3316ed227fb7bfe98e2f2bd)
| -rw-r--r-- | src/gallium/drivers/radeonsi/r600_texture.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 14 |
2 files changed, 10 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c index 91604395f1a..153df00639f 100644 --- a/src/gallium/drivers/radeonsi/r600_texture.c +++ b/src/gallium/drivers/radeonsi/r600_texture.c @@ -150,8 +150,7 @@ static int r600_init_surface(struct r600_screen *rscreen, surface->flags |= RADEON_SURF_SCANOUT; } - if ((ptex->bind & PIPE_BIND_DEPTH_STENCIL) && - !is_flushed_depth && is_depth) { + if (!is_flushed_depth && is_depth) { surface->flags |= RADEON_SURF_ZBUFFER; if (is_stencil) { diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 1eae9b013df..21399bf3622 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2064,6 +2064,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx unsigned char state_swizzle[4], swizzle[4]; unsigned height, depth, width; enum pipe_format pipe_format = state->format; + struct radeon_surface_level *surflevel; int first_non_void; uint64_t va; @@ -2083,6 +2084,8 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx state_swizzle[2] = state->swizzle_b; state_swizzle[3] = state->swizzle_a; + surflevel = tmp->surface.level; + /* Texturing with separate depth and stencil. */ if (tmp->is_depth && !tmp->is_flushing_texture) { switch (pipe_format) { @@ -2098,6 +2101,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx case PIPE_FORMAT_S8X24_UINT: case PIPE_FORMAT_X32_S8X24_UINT: pipe_format = PIPE_FORMAT_S8_UINT; + surflevel = tmp->surface.stencil_level; break; default:; } @@ -2170,10 +2174,10 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx /* not supported any more */ //endian = si_colorformat_endian_swap(format); - width = tmp->surface.level[0].npix_x; - height = tmp->surface.level[0].npix_y; - depth = tmp->surface.level[0].npix_z; - pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(pipe_format); + width = surflevel[0].npix_x; + height = surflevel[0].npix_y; + depth = surflevel[0].npix_z; + pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format); if (texture->target == PIPE_TEXTURE_1D_ARRAY) { height = 1; @@ -2183,7 +2187,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx } va = r600_resource_va(ctx->screen, texture); - va += tmp->surface.level[0].offset; + va += surflevel[0].offset; view->state[0] = va >> 8; view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | S_008F14_DATA_FORMAT(format) | |