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authorRob Clark <robdclark@gmail.com>2019-01-03 09:27:58 -0500
committerRob Clark <robdclark@gmail.com>2019-01-10 14:21:39 -0500
commitc92c18c70caf22eb9d733d8037da736ee78d5cf6 (patch)
tree89c961642a833af23d9f1f2a2e3626e0b8955d39
parenteb625d30b7b01db98b28a97ab6c15c9d3459fa74 (diff)
freedreno/a6xx: move tile_mode to sampler-view CSO
This is known when the CSO is created, so no need to patch it in later. Also, it seems like smaller textures where the first level is small enough to be linear, it seems like we should set linear tile mode. See: dEQP-GLES3.functional.texture.format.unsized.rgb_unsigned_byte_3d_pot Signed-off-by: Rob Clark <robdclark@gmail.com>
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_emit.c7
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_texture.c7
2 files changed, 7 insertions, 7 deletions
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 245353ee162..711ff4ac66c 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -394,13 +394,8 @@ fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
static const struct fd6_pipe_sampler_view dummy_view = {};
const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
- enum a6xx_tile_mode tile_mode = TILE6_LINEAR;
- if (view->base.texture)
- tile_mode = fd_resource(view->base.texture)->tile_mode;
-
- OUT_RING(state, view->texconst0 |
- A6XX_TEX_CONST_0_TILE_MODE(tile_mode));
+ OUT_RING(state, view->texconst0);
OUT_RING(state, view->texconst1);
OUT_RING(state, view->texconst2);
OUT_RING(state, view->texconst3);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
index b9121523b7c..e516e94b0d9 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c
@@ -281,12 +281,17 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
so->offset = cso->u.buf.offset;
} else {
unsigned miplevels;
+ enum a6xx_tile_mode tile_mode = TILE6_LINEAR;
lvl = fd_sampler_first_level(cso);
miplevels = fd_sampler_last_level(cso) - lvl;
layers = cso->u.tex.last_layer - cso->u.tex.first_layer + 1;
- so->texconst0 |= A6XX_TEX_CONST_0_MIPLVLS(miplevels);
+ if (!fd_resource_level_linear(prsc, lvl))
+ tile_mode = fd_resource(prsc)->tile_mode;
+
+ so->texconst0 |= A6XX_TEX_CONST_0_MIPLVLS(miplevels) |
+ A6XX_TEX_CONST_0_TILE_MODE(tile_mode);
so->texconst1 =
A6XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
A6XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));