diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2020-09-15 10:54:05 -0700 |
|---|---|---|
| committer | Dylan Baker <dylan.c.baker@intel.com> | 2020-11-19 11:04:48 -0800 |
| commit | b6033734486b16ffac74b1eea5a8ea7e8a4a1815 (patch) | |
| tree | f9850e9737f8445c4c5a3d37041f9a2fb0b19747 | |
| parent | 6b6f850afdbbe4a7df1628a4b5b951719ba15997 (diff) | |
intel/fs: Fix sampler message headers on Gen11+ when using scratch
Icelake's sampler message header introduces a field in m0.3 bit 0
which controls whether the sampler state pointer should be relative
to bindless sampler state base address or dynamic state base address.
g0.3 bit 0 is part of the per-thread scratch space field. On older
hardware, we were able to copy that along because the sampler ignored
bits 4:0. Now, however, we need to mask them out.
Fixes various textureGatherOffsets piglit tests when forcing the FS
to run with 2048 bytes of per-thread scratch space (which is a
per-thread scratch space encoding of 1, meaning bit 0 will be set).
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6735>
(cherry picked from commit 31290f98061acc237ba0f5d9c8c4c38ad6075c70)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_fs.cpp | 27 |
2 files changed, 23 insertions, 6 deletions
diff --git a/.pick_status.json b/.pick_status.json index c98f59dcd6e..b67f1ee208c 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -229,7 +229,7 @@ "description": "intel/fs: Fix sampler message headers on Gen11+ when using scratch", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": null }, diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 602f1b46a30..7ff3ef5590b 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -4987,21 +4987,38 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op, */ ubld1.MOV(component(header, 3), sampler_handle); } else if (is_high_sampler(devinfo, sampler)) { + fs_reg sampler_state_ptr = + retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD); + + /* Gen11+ sampler message headers include bits in 4:0 which conflict + * with the ones included in g0.3 bits 4:0. Mask them out. + */ + if (devinfo->gen >= 11) { + sampler_state_ptr = ubld1.vgrf(BRW_REGISTER_TYPE_UD); + ubld1.AND(sampler_state_ptr, + retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD), + brw_imm_ud(INTEL_MASK(31, 5))); + } + if (sampler.file == BRW_IMMEDIATE_VALUE) { assert(sampler.ud >= 16); const int sampler_state_size = 16; /* 16 bytes */ - ubld1.ADD(component(header, 3), - retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD), + ubld1.ADD(component(header, 3), sampler_state_ptr, brw_imm_ud(16 * (sampler.ud / 16) * sampler_state_size)); } else { fs_reg tmp = ubld1.vgrf(BRW_REGISTER_TYPE_UD); ubld1.AND(tmp, sampler, brw_imm_ud(0x0f0)); ubld1.SHL(tmp, tmp, brw_imm_ud(4)); - ubld1.ADD(component(header, 3), - retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD), - tmp); + ubld1.ADD(component(header, 3), sampler_state_ptr, tmp); } + } else if (devinfo->gen >= 11) { + /* Gen11+ sampler message headers include bits in 4:0 which conflict + * with the ones included in g0.3 bits 4:0. Mask them out. + */ + ubld1.AND(component(header, 3), + retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD), + brw_imm_ud(INTEL_MASK(31, 5))); } } |