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authorDaniel Schürmann <daniel@schuermann.dev>2019-11-29 16:43:24 +0100
committerDaniel Schürmann <daniel@schuermann.dev>2019-11-29 21:54:27 +0100
commit8861a82be7df2a5816254b45d390ddafad7d8711 (patch)
tree38443f9b0e41c0941f250baf4eae1f5ce6c8ec34
parent73783ed38914c697163e5c0e44e88db0494fac1b (diff)
aco: don't split live-ranges of linear VGPRs
Fixes: 93c8ebfa780ebd1495095e794731881aef29e7d3 'aco: Initial commit of independent AMD compiler' Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
-rw-r--r--src/amd/compiler/aco_register_allocation.cpp15
1 files changed, 11 insertions, 4 deletions
diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index c90c91a0325..c4144cc42f0 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -759,11 +759,18 @@ PhysReg get_reg_create_vector(ra_ctx& ctx,
/* count variables to be moved and check war_hint */
bool war_hint = false;
- for (unsigned j = reg_lo; j <= reg_hi; j++) {
- if (reg_file[j] != 0)
+ bool linear_vgpr = false;
+ for (unsigned j = reg_lo; j <= reg_hi && !linear_vgpr; j++) {
+ if (reg_file[j] != 0) {
k++;
+ /* we cannot split live ranges of linear vgprs */
+ if (ctx.assignments[reg_file[j]].second & (1 << 6))
+ linear_vgpr = true;
+ }
war_hint |= ctx.war_hint[j];
}
+ if (linear_vgpr || (war_hint && !best_war_hint))
+ continue;
/* count operands in wrong positions */
for (unsigned j = 0, offset = 0; j < instr->operands.size(); offset += instr->operands[j].size(), j++) {
@@ -775,7 +782,7 @@ PhysReg get_reg_create_vector(ra_ctx& ctx,
k += instr->operands[j].size();
}
bool aligned = rc == RegClass::v4 && reg_lo % 4 == 0;
- if (k > num_moves || (!aligned && k == num_moves) || (war_hint && !best_war_hint))
+ if (k > num_moves || (!aligned && k == num_moves))
continue;
best_pos = reg_lo;
@@ -961,7 +968,7 @@ void register_allocation(Program *program, std::vector<std::set<Temp>> live_out_
handle_live_in = [&](Temp val, Block *block) -> Temp {
std::vector<unsigned>& preds = val.is_linear() ? block->linear_preds : block->logical_preds;
- if (preds.size() == 0 && block->index != 0) {
+ if (preds.size() == 0 || val.regClass() == val.regClass().as_linear()) {
renames[block->index][val.id()] = val;
return val;
}