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authorChristian König <christian.koenig@amd.com>2014-08-24 12:22:08 +0200
committerChristian König <christian.koenig@amd.com>2014-08-26 17:56:57 +0200
commit80771e47b6c1e47ab55f17311e1d4e227a9eb3d8 (patch)
treeb2b7aa1e1dfcbb0a8988bd9c03afd7d813d0f08c
parent03a99ba9e41ea86355a4febbe0b1a114d5455b9f (diff)
radeon/uvd: fix field handling on R6XX style UVD
The first UVD generation can only do frame based output. Signed-off-by: Christian König <christian.koenig@amd.com>
-rw-r--r--src/gallium/drivers/radeon/radeon_video.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
index 17e9a59d81d..6dcee453348 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -251,8 +251,11 @@ int rvid_get_video_param(struct pipe_screen *screen,
profile != PIPE_VIDEO_PROFILE_VC1_MAIN;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
- /* and MPEG2 only with shaders */
- return codec != PIPE_VIDEO_FORMAT_MPEG12;
+ /* MPEG2 only with shaders and no support for
+ interlacing on R6xx style UVD */
+ return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
+ /* TODO: RV770 might actually work */
+ rscreen->family > CHIP_RV770;
default:
break;
}