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authorAlex Deucher <alexander.deucher@amd.com>2015-10-22 12:24:42 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-10-22 16:22:44 -0400
commit7b636581253fe858ac883e3d3eec21173ac069d4 (patch)
tree6d871bd91f387449378542c8334d7d0973b80e70
parent8cf84a7e470dbd3b46ce4081459d2ecfab22c2d5 (diff)
radeon/uvd: don't expose HEVC on old UVD hw (v3)
The section for UVD 2 and older was not updated when HEVC support was added. Reported by Kano on irc. v2: integrate the UVD2 and older checks into the main switch statement. v3: handle encode checking as well. Encode is already checked in the top case statement, so drop encode checks in the lower case statement. Reviewed-by: Christian K├Ânig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: mesa-stable@lists.freedesktop.org
-rw-r--r--src/gallium/drivers/radeon/radeon_video.c50
1 files changed, 18 insertions, 32 deletions
diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
index 3a1834b948f..32bfc32073b 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -205,11 +205,12 @@ int rvid_get_video_param(struct pipe_screen *screen,
enum pipe_video_cap param)
{
struct r600_common_screen *rscreen = (struct r600_common_screen *)screen;
+ enum pipe_video_format codec = u_reduce_video_profile(profile);
if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
- return u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
+ return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
rvce_is_fw_version_supported(rscreen);
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
@@ -232,38 +233,19 @@ int rvid_get_video_param(struct pipe_screen *screen,
}
}
- /* UVD 2.x limits */
- if (rscreen->family < CHIP_PALM) {
- enum pipe_video_format codec = u_reduce_video_profile(profile);
- switch (param) {
- case PIPE_VIDEO_CAP_SUPPORTED:
- /* no support for MPEG4 */
- return codec != PIPE_VIDEO_FORMAT_MPEG4 &&
- /* FIXME: VC-1 simple/main profile is broken */
- profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE &&
- profile != PIPE_VIDEO_PROFILE_VC1_MAIN;
- case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
- case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
- /* MPEG2 only with shaders and no support for
- interlacing on R6xx style UVD */
- return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
- rscreen->family > CHIP_RV770;
- default:
- break;
- }
- }
-
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
- switch (u_reduce_video_profile(profile)) {
+ switch (codec) {
case PIPE_VIDEO_FORMAT_MPEG12:
case PIPE_VIDEO_FORMAT_MPEG4:
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
- return entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE;
+ if (rscreen->family < CHIP_PALM)
+ /* no support for MPEG4 */
+ return codec != PIPE_VIDEO_FORMAT_MPEG4;
+ return true;
case PIPE_VIDEO_FORMAT_VC1:
/* FIXME: VC-1 simple/main profile is broken */
- return profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED &&
- entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE;
+ return profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED;
case PIPE_VIDEO_FORMAT_HEVC:
/* Carrizo only supports HEVC Main */
return rscreen->family >= CHIP_CARRIZO &&
@@ -280,13 +262,17 @@ int rvid_get_video_param(struct pipe_screen *screen,
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
- if (u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_HEVC)
- return false; //The hardware doesn't support interlaced HEVC.
- return true;
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
- if (u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_HEVC)
- return false; //The hardware doesn't support interlaced HEVC.
- return true;
+ if (rscreen->family < CHIP_PALM) {
+ /* MPEG2 only with shaders and no support for
+ interlacing on R6xx style UVD */
+ return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
+ rscreen->family > CHIP_RV770;
+ } else {
+ if (u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_HEVC)
+ return false; //The firmware doesn't support interlaced HEVC.
+ return true;
+ }
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
return true;
case PIPE_VIDEO_CAP_MAX_LEVEL: