diff options
| author | Danylo Piliaiev <dpiliaiev@igalia.com> | 2021-11-03 14:05:23 +0200 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2021-11-03 16:09:23 +0000 |
| commit | 79fcd63bd60ac46249c6dfcfa0eeef296ea3d04a (patch) | |
| tree | 49b98e24715554e0e36307540b96c83d034d5c44 | |
| parent | 675519f1d0eb26ecb5712a8bdbb82d7a92c07ed7 (diff) | |
tu: fix rast state allocation size on a6xx gen4
A few regs were added without changing the size of draw state.
Fixes: 4e05338d99abbf2858a0d8444ffc53028fe23051 ("turnip: Rast updates for a6xx gen4")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13644>
| -rw-r--r-- | src/freedreno/vulkan/tu_pipeline.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index 0072562e220..dc8d663a2c6 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -2779,7 +2779,9 @@ tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder, } struct tu_cs cs; - uint32_t cs_size = 9 + (builder->emit_msaa_state ? 11 : 0); + uint32_t cs_size = 9 + + (builder->device->physical_device->info->a6xx.has_shading_rate ? 8 : 0) + + (builder->emit_msaa_state ? 11 : 0); pipeline->rast_state = tu_cs_draw_state(&pipeline->cs, &cs, cs_size); tu_cs_emit_regs(&cs, |