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authorMarek Olšák <maraeo@gmail.com>2012-01-29 23:13:39 +0100
committerMarek Olšák <maraeo@gmail.com>2012-01-31 23:12:30 +0100
commit78293b99b23268e6698f1267aaf40647c17d95a5 (patch)
tree2c138dcd60528497f9b78de46cc68e1f27a90568
parentffe376d5a74dee837dc1a421de29ae551087630f (diff)
r600g: remove u8,u16,u32,u64 types
-rw-r--r--src/gallium/drivers/r600/evergreen_hw_context.c6
-rw-r--r--src/gallium/drivers/r600/evergreen_state.c6
-rw-r--r--src/gallium/drivers/r600/r600.h51
-rw-r--r--src/gallium/drivers/r600/r600_asm.c4
-rw-r--r--src/gallium/drivers/r600/r600_asm.h6
-rw-r--r--src/gallium/drivers/r600/r600_hw_context.c18
-rw-r--r--src/gallium/drivers/r600/r600_pipe.h2
-rw-r--r--src/gallium/drivers/r600/r600_shader.c10
-rw-r--r--src/gallium/drivers/r600/r600_state.c8
-rw-r--r--src/gallium/drivers/r600/r600_state_common.c6
10 files changed, 56 insertions, 61 deletions
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index f732ea38913..5f2f3bb539b 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -847,7 +847,7 @@ static int r600_resource_range_init(struct r600_context *ctx, struct r600_range
}
/* SHADER SAMPLER R600/R700 */
-static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
+static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
{
struct r600_reg r600_shader_sampler[] = {
{R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
@@ -863,7 +863,7 @@ static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
}
/* SHADER SAMPLER BORDER EG/CM */
-static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 offset, unsigned id)
+static int evergreen_state_sampler_border_init(struct r600_context *ctx, uint32_t offset, unsigned id)
{
struct r600_reg r600_shader_sampler_border[] = {
{R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0},
@@ -893,7 +893,7 @@ static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 off
return 0;
}
-static int evergreen_loop_const_init(struct r600_context *ctx, u32 offset)
+static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
{
unsigned nreg = 32;
struct r600_reg r600_loop_consts[32];
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 248411021f8..72ce29c579c 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -718,7 +718,7 @@ static void *evergreen_create_blend_state(struct pipe_context *ctx,
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
struct r600_pipe_state *rstate;
- u32 color_control, target_mask;
+ uint32_t color_control, target_mask;
/* FIXME there is more then 8 framebuffer */
unsigned blend_cntl[8];
@@ -1248,7 +1248,7 @@ static void evergreen_set_scissor_state(struct pipe_context *ctx,
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 tl, br;
+ uint32_t tl, br;
if (rstate == NULL)
return;
@@ -1519,7 +1519,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 shader_mask, tl, br;
+ uint32_t shader_mask, tl, br;
int tl_x, tl_y, br_x, br_y;
if (rstate == NULL)
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 515d122ce35..8614bea5888 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -33,11 +33,6 @@
#define R600_ERR(fmt, args...) \
fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args)
-typedef uint64_t u64;
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
struct winsys_handle;
enum radeon_family {
@@ -110,11 +105,11 @@ struct r600_resource {
#define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
struct r600_pipe_reg {
- u32 value;
+ uint32_t value;
struct r600_block *block;
struct r600_resource *bo;
enum radeon_bo_usage bo_usage;
- u32 id;
+ uint32_t id;
};
struct r600_pipe_state {
@@ -125,7 +120,7 @@ struct r600_pipe_state {
struct r600_pipe_resource_state {
unsigned id;
- u32 val[8];
+ uint32_t val[8];
struct r600_resource *bo[2];
enum radeon_bo_usage bo_usage[2];
};
@@ -153,10 +148,10 @@ struct r600_block {
unsigned pm4_ndwords;
unsigned pm4_flush_ndwords;
unsigned nbo;
- u16 nreg;
- u16 nreg_dirty;
- u32 *reg;
- u32 pm4[R600_BLOCK_MAX_REG];
+ uint16_t nreg;
+ uint16_t nreg_dirty;
+ uint32_t *reg;
+ uint32_t pm4[R600_BLOCK_MAX_REG];
unsigned pm4_bo_index[R600_BLOCK_MAX_REG];
struct r600_block_reloc reloc[R600_BLOCK_MAX_BO];
};
@@ -224,7 +219,7 @@ struct r600_context {
unsigned creloc;
struct r600_resource **bo;
- u32 *pm4;
+ uint32_t *pm4;
unsigned pm4_cdwords;
/* The list of active queries. Only one query of each type can be active. */
@@ -243,19 +238,19 @@ struct r600_context {
int num_ps_resources, num_vs_resources, num_fs_resources;
boolean have_depth_texture, have_depth_fb;
- unsigned num_so_targets;
- struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
- boolean streamout_start;
- unsigned streamout_append_bitmask;
- unsigned *vs_so_stride_in_dw;
+ unsigned num_so_targets;
+ struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
+ boolean streamout_start;
+ unsigned streamout_append_bitmask;
+ unsigned *vs_so_stride_in_dw;
};
struct r600_draw {
- u32 vgt_num_indices;
- u32 vgt_num_instances;
- u32 vgt_index_type;
- u32 vgt_draw_initiator;
- u32 indices_bo_offset;
+ uint32_t vgt_num_indices;
+ uint32_t vgt_num_instances;
+ uint32_t vgt_index_type;
+ uint32_t vgt_draw_initiator;
+ uint32_t indices_bo_offset;
unsigned db_render_override;
unsigned db_render_control;
struct r600_resource *indices;
@@ -304,27 +299,27 @@ void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struc
void _r600_pipe_state_add_reg(struct r600_context *ctx,
struct r600_pipe_state *state,
- u32 offset, u32 value,
- u32 range_id, u32 block_id,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id,
struct r600_resource *bo,
enum radeon_bo_usage usage);
void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
- u32 offset, u32 value,
+ uint32_t offset, uint32_t value,
struct r600_resource *bo,
enum radeon_bo_usage usage);
#define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state,
- u32 value)
+ uint32_t value)
{
state->regs[state->nregs].value = value;
state->nregs++;
}
static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state,
- u32 value, struct r600_resource *bo,
+ uint32_t value, struct r600_resource *bo,
enum radeon_bo_usage usage)
{
state->regs[state->nregs].value = value;
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index b78d64e227d..c690c9bccff 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -941,7 +941,7 @@ static int replace_gpr_with_pv_ps(struct r600_bytecode *bc,
return 0;
}
-void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg)
+void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg)
{
switch(value) {
case 0:
@@ -2712,7 +2712,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
const struct util_format_description *desc;
unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
unsigned format, num_format, format_comp, endian;
- u32 *bytecode;
+ uint32_t *bytecode;
int i, r;
/* Vertex element offsets need special handling. If the offset is
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index a68b299c713..3d6544b2e39 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -194,8 +194,8 @@ struct r600_bytecode {
unsigned nstack;
unsigned nresource;
unsigned force_add_cf;
- u32 *bytecode;
- u32 fc_sp;
+ uint32_t *bytecode;
+ uint32_t fc_sp;
struct r600_cf_stack_entry fc_stack[32];
unsigned call_sp;
struct r600_cf_callstack callstack[SQ_MAX_CALL_DEPTH];
@@ -218,7 +218,7 @@ int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecod
int r600_bytecode_build(struct r600_bytecode *bc);
int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst);
int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type);
-void r600_bytecode_special_constants(u32 value, unsigned *sel, unsigned *neg);
+void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg);
void r600_bytecode_dump(struct r600_bytecode *bc);
int cm_bytecode_add_cf_end(struct r600_bytecode *bc);
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index 0d5fcb42d54..bb9d8fc3efc 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -35,7 +35,7 @@
void r600_get_backend_mask(struct r600_context *ctx)
{
struct r600_resource *buffer;
- u32 *results;
+ uint32_t *results;
unsigned num_backends = ctx->screen->info.r600_num_backends;
unsigned i, mask = 0;
@@ -109,7 +109,7 @@ void r600_get_backend_mask(struct r600_context *ctx)
err:
/* fallback to old method - set num_backends lower bits to 1 */
- ctx->backend_mask = (~((u32)0))>>(32-num_backends);
+ ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends);
return;
}
@@ -684,7 +684,7 @@ static int r600_resource_range_init(struct r600_context *ctx, struct r600_range
}
/* SHADER SAMPLER R600/R700 */
-static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
+static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset)
{
struct r600_reg r600_shader_sampler[] = {
{R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
@@ -700,7 +700,7 @@ static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
}
/* SHADER SAMPLER BORDER R600/R700 */
-static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
+static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset)
{
struct r600_reg r600_shader_sampler_border[] = {
{R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
@@ -716,7 +716,7 @@ static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
}
-static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
+static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset)
{
unsigned nreg = 32;
struct r600_reg r600_loop_consts[32];
@@ -1703,7 +1703,7 @@ static boolean r600_query_result(struct r600_context *ctx, struct r600_query *qu
void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
{
unsigned new_results_end, i;
- u32 *results;
+ uint32_t *results;
uint64_t va;
r600_need_cs_space(ctx, query->num_cs_dw * 2, TRUE);
@@ -1720,7 +1720,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
case PIPE_QUERY_OCCLUSION_PREDICATE:
results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
if (results) {
- results = (u32*)((char*)results + query->results_end);
+ results = (uint32_t*)((char*)results + query->results_end);
memset(results, 0, query->result_size);
/* Set top bits for unused backends */
@@ -1740,7 +1740,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
case PIPE_QUERY_SO_STATISTICS:
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE);
- results = (u32*)((char*)results + query->results_end);
+ results = (uint32_t*)((char*)results + query->results_end);
memset(results, 0, query->result_size);
ctx->ws->buffer_unmap(query->buffer->buf);
break;
@@ -1843,7 +1843,7 @@ void r600_query_predication(struct r600_context *ctx, struct r600_query *query,
} else {
unsigned results_base = query->results_start;
unsigned count;
- u32 op;
+ uint32_t op;
/* find count of the query data blocks */
count = (query->buffer->b.b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.b.width0;
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 4ba4b1bdad1..e1fa01fc177 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -389,7 +389,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
/*
* common helpers
*/
-static INLINE u32 S_FIXED(float value, u32 frac_bits)
+static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
{
return value * (1 << frac_bits);
}
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 6acd2160878..109830decd9 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -182,12 +182,12 @@ struct r600_shader_ctx {
unsigned file_offset[TGSI_FILE_COUNT];
unsigned temp_reg;
struct r600_shader_tgsi_instruction *inst_info;
- struct r600_bytecode *bc;
+ struct r600_bytecode *bc;
struct r600_shader *shader;
struct r600_shader_src src[4];
- u32 *literals;
- u32 nliterals;
- u32 max_driver_temp_used;
+ uint32_t *literals;
+ uint32_t nliterals;
+ uint32_t max_driver_temp_used;
/* needed for evergreen interpolation */
boolean input_centroid;
boolean input_linear;
@@ -3277,7 +3277,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
const boolean src_requires_loading = tgsi_tex_src_requires_loading(ctx, 0);
boolean src_loaded = FALSE;
unsigned sampler_src_reg = 1;
- u8 offset_x = 0, offset_y = 0, offset_z = 0;
+ uint8_t offset_x = 0, offset_y = 0, offset_z = 0;
src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 42ed14abd23..f349541d5ff 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -774,7 +774,7 @@ static void *r600_create_blend_state(struct pipe_context *ctx,
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
struct r600_pipe_state *rstate;
- u32 color_control = 0, target_mask;
+ uint32_t color_control = 0, target_mask;
if (blend == NULL) {
return NULL;
@@ -1363,7 +1363,7 @@ static void r600_set_scissor_state(struct pipe_context *ctx,
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 tl, br;
+ uint32_t tl, br;
if (rstate == NULL)
return;
@@ -1605,7 +1605,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
- u32 shader_mask, tl, br, shader_control;
+ uint32_t shader_mask, tl, br, shader_control;
if (rstate == NULL)
return;
@@ -1816,7 +1816,7 @@ void r600_init_config(struct r600_pipe_context *rctx)
int num_es_stack_entries;
enum radeon_family family;
struct r600_pipe_state *rstate = &rctx->config;
- u32 tmp;
+ uint32_t tmp;
family = rctx->family;
ps_prio = 0;
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 5b54a00306e..7d7daafea82 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -802,8 +802,8 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
void _r600_pipe_state_add_reg(struct r600_context *ctx,
struct r600_pipe_state *state,
- u32 offset, u32 value,
- u32 range_id, u32 block_id,
+ uint32_t offset, uint32_t value,
+ uint32_t range_id, uint32_t block_id,
struct r600_resource *bo,
enum radeon_bo_usage usage)
{
@@ -826,7 +826,7 @@ void _r600_pipe_state_add_reg(struct r600_context *ctx,
}
void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
- u32 offset, u32 value,
+ uint32_t offset, uint32_t value,
struct r600_resource *bo,
enum radeon_bo_usage usage)
{