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authorAlex Deucher <alexander.deucher@amd.com>2012-02-10 11:02:03 -0500
committerAlex Deucher <alexander.deucher@amd.com>2012-02-10 11:31:23 -0500
commit5e1495b2d9311fa2b320766a1d299053904bd9c3 (patch)
tree3c2a46da24d2f7588e2b1618af5841f0e113d3c2
parentacca690c259824636ef1ff684a10bd1caca4751f (diff)
r600g: 128 bit formats require tile_type = 1 on cayman
Noticed by taiu on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Note: this is a candidate for the stable branches.
-rw-r--r--src/gallium/drivers/r600/evergreen_state.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 56a497b081b..b8825163161 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1174,6 +1174,11 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
bankw = eg_bank_wh(bankw);
bankh = eg_bank_wh(bankh);
}
+ /* 128 bit formats require tile type = 1 */
+ if (rscreen->chip_class == CAYMAN) {
+ if (util_format_get_blocksize(state->format) >= 16)
+ tile_type = 1;
+ }
nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
@@ -1511,6 +1516,11 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta
bankw = eg_bank_wh(bankw);
bankh = eg_bank_wh(bankh);
}
+ /* 128 bit formats require tile type = 1 */
+ if (rscreen->chip_class == CAYMAN) {
+ if (util_format_get_blocksize(surf->base.format) >= 16)
+ tile_type = 1;
+ }
nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
desc = util_format_description(surf->base.format);
for (i = 0; i < 4; i++) {