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authorJose Maria Casanova Crespo <jmcasanova@igalia.com>2020-10-15 13:22:28 +0200
committerJose Maria Casanova Crespo <jmcasanova@igalia.com>2020-10-15 22:05:58 +0200
commit4cfdd425b65411a3a558748b4c2041783e95aa18 (patch)
treed7fa933d26f2e5fba2c33eadef824b42aac3b951
parentf91b2fe384a38d74df014c6421156a9f8b0bb78e (diff)
vc4: Add missing load_ubo set_align in yuv_blit fs.
Fixes: e78a7a18252 ("nir: Assert memory loads are aligned") Reviewed-by: Eric Anholt <eric@anholt.net> Tested-by: Piotr Oniszczuk <piotr.oniszczuk@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7160>
-rw-r--r--src/gallium/drivers/vc4/vc4_blit.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/vc4/vc4_blit.c b/src/gallium/drivers/vc4/vc4_blit.c
index 4e4c4898ea8..e72e5dc12ba 100644
--- a/src/gallium/drivers/vc4/vc4_blit.c
+++ b/src/gallium/drivers/vc4/vc4_blit.c
@@ -299,6 +299,7 @@ static void *vc4_get_yuv_fs(struct pipe_context *pctx, int cpp)
nir_ssa_dest_init(&load->instr, &load->dest, load->num_components, 32, NULL);
load->src[0] = nir_src_for_ssa(one);
load->src[1] = nir_src_for_ssa(nir_iadd(&b, x_offset, y_offset));
+ nir_intrinsic_set_align(load, 4, 0);
nir_builder_instr_insert(&b, &load->instr);
nir_store_var(&b, color_out,