diff options
| author | Christian König <christian.koenig@amd.com> | 2017-03-08 12:51:13 +0100 |
|---|---|---|
| committer | Christian König <christian.koenig@amd.com> | 2017-03-13 08:51:25 +0100 |
| commit | 3e1e441aa05069e3eee906144cf96898e0b802e2 (patch) | |
| tree | 66c7febaf60bd730aeb2e86c0dc28e04f7afdf42 | |
| parent | cee591a224466f344cf6ab504c66f527d4f95b6d (diff) | |
radeon/UVD: fix the decoding target pitch calculation
The firmware expects the value in pixel not bytes. Didn't made a difference
so far because we only used 8bpp surfaces.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Mark Thompson <sw@jkqxz.net>
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_uvd.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index f1339d121b7..7a08c81cbc0 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.c +++ b/src/gallium/drivers/radeon/radeon_uvd.c @@ -1354,7 +1354,7 @@ static unsigned bank_wh(unsigned bankwh) void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma, struct radeon_surf *chroma) { - msg->body.decode.dt_pitch = luma->level[0].nblk_x * luma->bpe; + msg->body.decode.dt_pitch = luma->level[0].nblk_x; switch (luma->level[0].mode) { case RADEON_SURF_MODE_LINEAR_ALIGNED: msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR; |