summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorEdward O'Callaghan <funfunctor@folklore1984.net>2016-12-06 11:07:13 +1100
committerEdward O'Callaghan <funfunctor@folklore1984.net>2017-02-03 16:13:46 +1100
commit38794259175852084532499a09dec85b6c6a4321 (patch)
tree0326c96b6c17166f712621b7976edea8591043fc
parentd77fa310ed8fb54aafc017eae844a51407ca907c (diff)
ilo: EOL unmaintained older gallium intel driver
This is no longer actively maintained and is just accumulating bitrot. Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net> Acked-by: Chia-I Wu <olvaffe@gmail.com>
-rw-r--r--src/gallium/drivers/ilo/Android.mk35
-rw-r--r--src/gallium/drivers/ilo/Automake.inc11
-rw-r--r--src/gallium/drivers/ilo/Makefile.am33
-rw-r--r--src/gallium/drivers/ilo/Makefile.sources120
-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder.c497
-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder.h557
-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder_3d.h96
-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder_3d_bottom.h1118
-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder_3d_top.h1476
-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder_blt.h322
-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder_decode.c685
-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder_media.h217
-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder_mi.h220
-rw-r--r--src/gallium/drivers/ilo/core/ilo_builder_render.h303
-rw-r--r--src/gallium/drivers/ilo/core/ilo_core.h35
-rw-r--r--src/gallium/drivers/ilo/core/ilo_debug.c51
-rw-r--r--src/gallium/drivers/ilo/core/ilo_debug.h122
-rw-r--r--src/gallium/drivers/ilo/core/ilo_dev.c181
-rw-r--r--src/gallium/drivers/ilo/core/ilo_dev.h78
-rw-r--r--src/gallium/drivers/ilo/core/ilo_image.c1451
-rw-r--r--src/gallium/drivers/ilo/core/ilo_image.h361
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_cc.c890
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_cc.h199
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_compute.c476
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_compute.h100
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_raster.c1248
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_raster.h301
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_sampler.c742
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_sampler.h103
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_sbe.c350
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_sbe.h103
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_shader.c763
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_shader.h295
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_shader_ps.c772
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_sol.c467
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_sol.h166
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_surface.c1270
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_surface.h128
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_surface_format.c351
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_urb.c769
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_urb.h103
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_vf.c1000
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_vf.h230
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_viewport.c378
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_viewport.h132
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_zs.c677
-rw-r--r--src/gallium/drivers/ilo/core/ilo_state_zs.h85
-rw-r--r--src/gallium/drivers/ilo/core/ilo_vma.h73
-rw-r--r--src/gallium/drivers/ilo/core/intel_winsys.h329
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_blitter.xml.h129
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h563
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h332
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_mi.xml.h358
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_regs.xml.h183
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_render.xml.h310
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h1945
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_render_dynamic.xml.h532
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_render_media.xml.h315
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h533
-rw-r--r--src/gallium/drivers/ilo/genhw/genhw.h257
-rw-r--r--src/gallium/drivers/ilo/ilo_blit.c254
-rw-r--r--src/gallium/drivers/ilo/ilo_blit.h185
-rw-r--r--src/gallium/drivers/ilo/ilo_blitter.c74
-rw-r--r--src/gallium/drivers/ilo/ilo_blitter.h169
-rw-r--r--src/gallium/drivers/ilo/ilo_blitter_blt.c574
-rw-r--r--src/gallium/drivers/ilo/ilo_blitter_pipe.c226
-rw-r--r--src/gallium/drivers/ilo/ilo_blitter_rectlist.c510
-rw-r--r--src/gallium/drivers/ilo/ilo_common.h44
-rw-r--r--src/gallium/drivers/ilo/ilo_context.c216
-rw-r--r--src/gallium/drivers/ilo/ilo_context.h89
-rw-r--r--src/gallium/drivers/ilo/ilo_cp.c229
-rw-r--r--src/gallium/drivers/ilo/ilo_cp.h142
-rw-r--r--src/gallium/drivers/ilo/ilo_draw.c653
-rw-r--r--src/gallium/drivers/ilo/ilo_draw.h57
-rw-r--r--src/gallium/drivers/ilo/ilo_format.c356
-rw-r--r--src/gallium/drivers/ilo/ilo_format.h203
-rw-r--r--src/gallium/drivers/ilo/ilo_gpgpu.c117
-rw-r--r--src/gallium/drivers/ilo/ilo_gpgpu.h38
-rw-r--r--src/gallium/drivers/ilo/ilo_public.h37
-rw-r--r--src/gallium/drivers/ilo/ilo_query.c244
-rw-r--r--src/gallium/drivers/ilo/ilo_query.h62
-rw-r--r--src/gallium/drivers/ilo/ilo_render.c504
-rw-r--r--src/gallium/drivers/ilo/ilo_render.h107
-rw-r--r--src/gallium/drivers/ilo/ilo_render_dynamic.c605
-rw-r--r--src/gallium/drivers/ilo/ilo_render_gen.h512
-rw-r--r--src/gallium/drivers/ilo/ilo_render_gen6.c984
-rw-r--r--src/gallium/drivers/ilo/ilo_render_gen7.c865
-rw-r--r--src/gallium/drivers/ilo/ilo_render_gen8.c386
-rw-r--r--src/gallium/drivers/ilo/ilo_render_media.c230
-rw-r--r--src/gallium/drivers/ilo/ilo_render_surface.c626
-rw-r--r--src/gallium/drivers/ilo/ilo_resource.c777
-rw-r--r--src/gallium/drivers/ilo/ilo_resource.h187
-rw-r--r--src/gallium/drivers/ilo/ilo_screen.c809
-rw-r--r--src/gallium/drivers/ilo/ilo_screen.h54
-rw-r--r--src/gallium/drivers/ilo/ilo_shader.c1458
-rw-r--r--src/gallium/drivers/ilo/ilo_shader.h181
-rw-r--r--src/gallium/drivers/ilo/ilo_state.c2629
-rw-r--r--src/gallium/drivers/ilo/ilo_state.h417
-rw-r--r--src/gallium/drivers/ilo/ilo_transfer.c1260
-rw-r--r--src/gallium/drivers/ilo/ilo_transfer.h77
-rw-r--r--src/gallium/drivers/ilo/ilo_video.c60
-rw-r--r--src/gallium/drivers/ilo/ilo_video.h38
-rw-r--r--src/gallium/drivers/ilo/shader/ilo_shader_cs.c222
-rw-r--r--src/gallium/drivers/ilo/shader/ilo_shader_fs.c1909
-rw-r--r--src/gallium/drivers/ilo/shader/ilo_shader_gs.c1455
-rw-r--r--src/gallium/drivers/ilo/shader/ilo_shader_internal.h261
-rw-r--r--src/gallium/drivers/ilo/shader/ilo_shader_vs.c1360
-rw-r--r--src/gallium/drivers/ilo/shader/toy_compiler.c557
-rw-r--r--src/gallium/drivers/ilo/shader/toy_compiler.h490
-rw-r--r--src/gallium/drivers/ilo/shader/toy_compiler_asm.c1225
-rw-r--r--src/gallium/drivers/ilo/shader/toy_compiler_disasm.c2151
-rw-r--r--src/gallium/drivers/ilo/shader/toy_compiler_reg.h800
-rw-r--r--src/gallium/drivers/ilo/shader/toy_helpers.h295
-rw-r--r--src/gallium/drivers/ilo/shader/toy_legalize.c641
-rw-r--r--src/gallium/drivers/ilo/shader/toy_legalize.h52
-rw-r--r--src/gallium/drivers/ilo/shader/toy_legalize_ra.c628
-rw-r--r--src/gallium/drivers/ilo/shader/toy_optimize.c71
-rw-r--r--src/gallium/drivers/ilo/shader/toy_optimize.h36
-rw-r--r--src/gallium/drivers/ilo/shader/toy_tgsi.c2517
-rw-r--r--src/gallium/drivers/ilo/shader/toy_tgsi.h166
120 files changed, 0 insertions, 58007 deletions
diff --git a/src/gallium/drivers/ilo/Android.mk b/src/gallium/drivers/ilo/Android.mk
deleted file mode 100644
index 420413402f4..00000000000
--- a/src/gallium/drivers/ilo/Android.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-# Mesa 3-D graphics library
-#
-# Copyright (C) 2013 LunarG Inc.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice shall be included
-# in all copies or substantial portions of the Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-# DEALINGS IN THE SOFTWARE.
-
-LOCAL_PATH := $(call my-dir)
-
-# get C_SOURCES
-include $(LOCAL_PATH)/Makefile.sources
-
-include $(CLEAR_VARS)
-
-LOCAL_SRC_FILES := $(C_SOURCES)
-
-LOCAL_MODULE := libmesa_pipe_ilo
-
-include $(GALLIUM_COMMON_MK)
-include $(BUILD_STATIC_LIBRARY)
diff --git a/src/gallium/drivers/ilo/Automake.inc b/src/gallium/drivers/ilo/Automake.inc
deleted file mode 100644
index 5124671180e..00000000000
--- a/src/gallium/drivers/ilo/Automake.inc
+++ /dev/null
@@ -1,11 +0,0 @@
-if HAVE_GALLIUM_ILO
-
-TARGET_DRIVERS += ilo
-TARGET_CPPFLAGS += -DGALLIUM_ILO
-TARGET_LIB_DEPS += \
- $(top_builddir)/src/gallium/winsys/intel/drm/libintelwinsys.la \
- $(top_builddir)/src/gallium/drivers/ilo/libilo.la \
- $(INTEL_LIBS) \
- $(LIBDRM_LIBS)
-
-endif
diff --git a/src/gallium/drivers/ilo/Makefile.am b/src/gallium/drivers/ilo/Makefile.am
deleted file mode 100644
index 1f14153748e..00000000000
--- a/src/gallium/drivers/ilo/Makefile.am
+++ /dev/null
@@ -1,33 +0,0 @@
-# Copyright © 2012 Intel Corporation
-# Copyright (C) 2013 LunarG, Inc.
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice (including the next
-# paragraph) shall be included in all copies or substantial portions of the
-# Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-# DEALINGS IN THE SOFTWARE.
-
-include Makefile.sources
-include $(top_srcdir)/src/gallium/Automake.inc
-
-AM_CPPFLAGS = \
- $(GALLIUM_DRIVER_CFLAGS)
-
-noinst_HEADERS = $(GENHW_FILES)
-noinst_LTLIBRARIES = libilo.la
-
-libilo_la_SOURCES = $(C_SOURCES)
diff --git a/src/gallium/drivers/ilo/Makefile.sources b/src/gallium/drivers/ilo/Makefile.sources
deleted file mode 100644
index 7a7db938f92..00000000000
--- a/src/gallium/drivers/ilo/Makefile.sources
+++ /dev/null
@@ -1,120 +0,0 @@
-C_SOURCES := \
- core/ilo_builder.c \
- core/ilo_builder.h \
- core/ilo_builder_3d.h \
- core/ilo_builder_3d_bottom.h \
- core/ilo_builder_3d_top.h \
- core/ilo_builder_blt.h \
- core/ilo_builder_decode.c \
- core/ilo_builder_media.h \
- core/ilo_builder_mi.h \
- core/ilo_builder_render.h \
- core/ilo_core.h \
- core/ilo_debug.c \
- core/ilo_debug.h \
- core/ilo_dev.c \
- core/ilo_dev.h \
- core/ilo_image.c \
- core/ilo_image.h \
- core/ilo_state_cc.c \
- core/ilo_state_cc.h \
- core/ilo_state_compute.c \
- core/ilo_state_compute.h \
- core/ilo_state_raster.c \
- core/ilo_state_raster.h \
- core/ilo_state_sampler.c \
- core/ilo_state_sampler.h \
- core/ilo_state_sbe.c \
- core/ilo_state_sbe.h \
- core/ilo_state_shader.c \
- core/ilo_state_shader_ps.c \
- core/ilo_state_shader.h \
- core/ilo_state_sol.c \
- core/ilo_state_sol.h \
- core/ilo_state_surface.c \
- core/ilo_state_surface_format.c \
- core/ilo_state_surface.h \
- core/ilo_state_urb.c \
- core/ilo_state_urb.h \
- core/ilo_state_vf.c \
- core/ilo_state_vf.h \
- core/ilo_state_viewport.c \
- core/ilo_state_viewport.h \
- core/ilo_state_zs.c \
- core/ilo_state_zs.h \
- core/ilo_vma.h \
- core/intel_winsys.h \
- ilo_blit.c \
- ilo_blit.h \
- ilo_blitter.c \
- ilo_blitter.h \
- ilo_blitter_blt.c \
- ilo_blitter_pipe.c \
- ilo_blitter_rectlist.c \
- ilo_common.h \
- ilo_context.c \
- ilo_context.h \
- ilo_cp.c \
- ilo_cp.h \
- ilo_draw.c \
- ilo_draw.h \
- ilo_format.c \
- ilo_format.h \
- ilo_gpgpu.c \
- ilo_gpgpu.h \
- ilo_public.h \
- ilo_query.c \
- ilo_query.h \
- ilo_render.c \
- ilo_render.h \
- ilo_render_gen.h \
- ilo_render_dynamic.c \
- ilo_render_gen6.c \
- ilo_render_gen7.c \
- ilo_render_gen8.c \
- ilo_render_media.c \
- ilo_render_surface.c \
- ilo_resource.c \
- ilo_resource.h \
- ilo_screen.c \
- ilo_screen.h \
- ilo_shader.c \
- ilo_shader.h \
- ilo_state.c \
- ilo_state.h \
- ilo_transfer.c \
- ilo_transfer.h \
- ilo_video.c \
- ilo_video.h \
- \
- shader/ilo_shader_cs.c \
- shader/ilo_shader_fs.c \
- shader/ilo_shader_gs.c \
- shader/ilo_shader_internal.h \
- shader/ilo_shader_vs.c \
- shader/toy_compiler.c \
- shader/toy_compiler.h \
- shader/toy_compiler_asm.c \
- shader/toy_compiler_disasm.c \
- shader/toy_compiler_reg.h \
- shader/toy_helpers.h \
- shader/toy_legalize.c \
- shader/toy_legalize.h \
- shader/toy_legalize_ra.c \
- shader/toy_optimize.c \
- shader/toy_optimize.h \
- shader/toy_tgsi.c \
- shader/toy_tgsi.h
-
-GENHW_FILES := \
- genhw/gen_blitter.xml.h \
- genhw/gen_eu_isa.xml.h \
- genhw/gen_eu_message.xml.h \
- genhw/genhw.h \
- genhw/gen_mi.xml.h \
- genhw/gen_regs.xml.h \
- genhw/gen_render.xml.h \
- genhw/gen_render_3d.xml.h \
- genhw/gen_render_dynamic.xml.h \
- genhw/gen_render_media.xml.h \
- genhw/gen_render_surface.xml.h
diff --git a/src/gallium/drivers/ilo/core/ilo_builder.c b/src/gallium/drivers/ilo/core/ilo_builder.c
deleted file mode 100644
index 079872f4306..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_builder.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_memory.h"
-
-#include "ilo_builder.h"
-#include "ilo_builder_render.h" /* for ilo_builder_batch_patch_sba() */
-
-enum ilo_builder_writer_flags {
- /*
- * When this bit is set, ilo_builder_begin() will not realllocate. New
- * data will be appended instead.
- */
- WRITER_FLAG_APPEND = 1 << 0,
-
- /*
- * When this bit is set, the writer grows when full. When not, callers
- * must make sure the writer never needs to grow.
- */
- WRITER_FLAG_GROW = 1 << 1,
-
- /*
- * The writer will be mapped directly.
- */
- WRITER_FLAG_MAP = 1 << 2,
-};
-
-/**
- * Set the initial size and flags of a writer.
- */
-static void
-ilo_builder_writer_init(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- switch (which) {
- case ILO_BUILDER_WRITER_BATCH:
- writer->size = sizeof(uint32_t) * 8192;
- break;
- case ILO_BUILDER_WRITER_INSTRUCTION:
- /*
- * The EUs pretch some instructions. But since the kernel invalidates
- * the instruction cache between batch buffers, we can set
- * WRITER_FLAG_APPEND without worrying the EUs would see invalid
- * instructions prefetched.
- */
- writer->flags = WRITER_FLAG_APPEND | WRITER_FLAG_GROW;
- writer->size = 8192;
- break;
- default:
- assert(!"unknown builder writer");
- return;
- break;
- }
-
- if (builder->dev->has_llc)
- writer->flags |= WRITER_FLAG_MAP;
-}
-
-/**
- * Free all resources used by a writer. Note that the initial size is not
- * reset.
- */
-static void
-ilo_builder_writer_reset(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- if (writer->ptr) {
- if (writer->flags & WRITER_FLAG_MAP)
- intel_bo_unmap(writer->bo);
- else
- FREE(writer->ptr);
-
- writer->ptr = NULL;
- }
-
- intel_bo_unref(writer->bo);
- writer->bo = NULL;
-
- writer->used = 0;
- writer->stolen = 0;
-
- if (writer->items) {
- FREE(writer->items);
- writer->item_alloc = 0;
- writer->item_used = 0;
- }
-}
-
-/**
- * Discard everything written so far.
- */
-void
-ilo_builder_writer_discard(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- intel_bo_truncate_relocs(writer->bo, 0);
- writer->used = 0;
- writer->stolen = 0;
- writer->item_used = 0;
-}
-
-static struct intel_bo *
-alloc_writer_bo(struct intel_winsys *winsys,
- enum ilo_builder_writer_type which,
- unsigned size)
-{
- static const char *writer_names[ILO_BUILDER_WRITER_COUNT] = {
- [ILO_BUILDER_WRITER_BATCH] = "batch",
- [ILO_BUILDER_WRITER_INSTRUCTION] = "instruction",
- };
-
- return intel_winsys_alloc_bo(winsys, writer_names[which], size, true);
-}
-
-static void *
-map_writer_bo(struct intel_bo *bo, unsigned flags)
-{
- assert(flags & WRITER_FLAG_MAP);
-
- if (flags & WRITER_FLAG_APPEND)
- return intel_bo_map_gtt_async(bo);
- else
- return intel_bo_map(bo, true);
-}
-
-/**
- * Allocate and map the buffer for writing.
- */
-static bool
-ilo_builder_writer_alloc_and_map(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- /* allocate a new bo when not appending */
- if (!(writer->flags & WRITER_FLAG_APPEND) || !writer->bo) {
- struct intel_bo *bo;
-
- bo = alloc_writer_bo(builder->winsys, which, writer->size);
- if (bo) {
- intel_bo_unref(writer->bo);
- writer->bo = bo;
- } else if (writer->bo) {
- /* reuse the old bo */
- ilo_builder_writer_discard(builder, which);
- } else {
- return false;
- }
-
- writer->used = 0;
- writer->stolen = 0;
- writer->item_used = 0;
- }
-
- /* map the bo or allocate the staging system memory */
- if (writer->flags & WRITER_FLAG_MAP)
- writer->ptr = map_writer_bo(writer->bo, writer->flags);
- else if (!writer->ptr)
- writer->ptr = MALLOC(writer->size);
-
- return (writer->ptr != NULL);
-}
-
-/**
- * Unmap the buffer for submission.
- */
-static bool
-ilo_builder_writer_unmap(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- unsigned offset;
- int err = 0;
-
- if (writer->flags & WRITER_FLAG_MAP) {
- intel_bo_unmap(writer->bo);
- writer->ptr = NULL;
- return true;
- }
-
- offset = builder->begin_used[which];
- if (writer->used > offset) {
- err = intel_bo_pwrite(writer->bo, offset, writer->used - offset,
- (char *) writer->ptr + offset);
- }
-
- if (writer->stolen && !err) {
- const unsigned offset = writer->size - writer->stolen;
- err = intel_bo_pwrite(writer->bo, offset, writer->stolen,
- (const char *) writer->ptr + offset);
- }
-
- /* keep writer->ptr */
-
- return !err;
-}
-
-/**
- * Grow a mapped writer to at least \p new_size.
- */
-bool
-ilo_builder_writer_grow(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned new_size, bool preserve)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- struct intel_bo *new_bo;
- void *new_ptr;
-
- if (!(writer->flags & WRITER_FLAG_GROW))
- return false;
-
- /* stolen data may already be referenced and cannot be moved */
- if (writer->stolen)
- return false;
-
- if (new_size < writer->size << 1)
- new_size = writer->size << 1;
- /* STATE_BASE_ADDRESS requires page-aligned buffers */
- new_size = align(new_size, 4096);
-
- new_bo = alloc_writer_bo(builder->winsys, which, new_size);
- if (!new_bo)
- return false;
-
- /* map and copy the data over */
- if (writer->flags & WRITER_FLAG_MAP) {
- new_ptr = map_writer_bo(new_bo, writer->flags);
-
- /*
- * When WRITER_FLAG_APPEND and WRITER_FLAG_GROW are both set, we may end
- * up copying between two GTT-mapped BOs. That is slow. The issue
- * could be solved by adding intel_bo_map_async(), or callers may choose
- * to manually grow the writer without preserving the data.
- */
- if (new_ptr && preserve)
- memcpy(new_ptr, writer->ptr, writer->used);
- } else if (preserve) {
- new_ptr = REALLOC(writer->ptr, writer->size, new_size);
- } else {
- new_ptr = MALLOC(new_size);
- }
-
- if (!new_ptr) {
- intel_bo_unref(new_bo);
- return false;
- }
-
- if (writer->flags & WRITER_FLAG_MAP)
- intel_bo_unmap(writer->bo);
- else if (!preserve)
- FREE(writer->ptr);
-
- intel_bo_unref(writer->bo);
-
- writer->size = new_size;
- writer->bo = new_bo;
- writer->ptr = new_ptr;
-
- return true;
-}
-
-/**
- * Record an item for later decoding.
- */
-bool
-ilo_builder_writer_record(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- enum ilo_builder_item_type type,
- unsigned offset, unsigned size)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- struct ilo_builder_item *item;
-
- if (writer->item_used == writer->item_alloc) {
- const unsigned new_alloc = (writer->item_alloc) ?
- writer->item_alloc << 1 : 256;
- struct ilo_builder_item *items;
-
- items = REALLOC(writer->items,
- sizeof(writer->items[0]) * writer->item_alloc,
- sizeof(writer->items[0]) * new_alloc);
- if (!items)
- return false;
-
- writer->items = items;
- writer->item_alloc = new_alloc;
- }
-
- item = &writer->items[writer->item_used++];
- item->type = type;
- item->offset = offset;
- item->size = size;
-
- return true;
-}
-
-/**
- * Initialize the builder.
- */
-void
-ilo_builder_init(struct ilo_builder *builder,
- const struct ilo_dev *dev,
- struct intel_winsys *winsys)
-{
- unsigned i;
-
- assert(ilo_is_zeroed(builder, sizeof(*builder)));
-
- builder->dev = dev;
- builder->winsys = winsys;
-
- /* gen6_SURFACE_STATE() may override this */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- builder->mocs = GEN8_MOCS_MT_WB | GEN8_MOCS_CT_L3;
- break;
- case ILO_GEN(7.5):
- case ILO_GEN(7):
- builder->mocs = GEN7_MOCS_L3_WB;
- break;
- default:
- builder->mocs = 0;
- break;
- }
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++)
- ilo_builder_writer_init(builder, i);
-}
-
-/**
- * Reset the builder and free all resources used. After resetting, the
- * builder behaves as if it is newly initialized, except for potentially
- * larger initial bo sizes.
- */
-void
-ilo_builder_reset(struct ilo_builder *builder)
-{
- unsigned i;
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++)
- ilo_builder_writer_reset(builder, i);
-}
-
-/**
- * Allocate and map the BOs. It may re-allocate or reuse existing BOs if
- * there is any.
- *
- * Most builder functions can only be called after ilo_builder_begin() and
- * before ilo_builder_end().
- */
-bool
-ilo_builder_begin(struct ilo_builder *builder)
-{
- unsigned i;
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++) {
- if (!ilo_builder_writer_alloc_and_map(builder, i)) {
- ilo_builder_reset(builder);
- return false;
- }
-
- builder->begin_used[i] = builder->writers[i].used;
- }
-
- builder->unrecoverable_error = false;
- builder->sba_instruction_pos = 0;
-
- return true;
-}
-
-/**
- * Unmap BOs and make sure the written data landed the BOs. The batch buffer
- * ready for submission is returned.
- */
-struct intel_bo *
-ilo_builder_end(struct ilo_builder *builder, unsigned *used)
-{
- struct ilo_builder_writer *bat;
- unsigned i;
-
- ilo_builder_batch_patch_sba(builder);
-
- assert(ilo_builder_validate(builder, 0, NULL));
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++) {
- if (!ilo_builder_writer_unmap(builder, i))
- builder->unrecoverable_error = true;
- }
-
- if (builder->unrecoverable_error)
- return NULL;
-
- bat = &builder->writers[ILO_BUILDER_WRITER_BATCH];
-
- *used = bat->used;
-
- return bat->bo;
-}
-
-/**
- * Return true if the builder is in a valid state, after accounting for the
- * additional BOs specified. The additional BOs can be listed to avoid
- * snapshotting and restoring when they are known ahead of time.
- *
- * The number of additional BOs should not be more than a few. Like two, for
- * copying between two BOs.
- *
- * Callers must make sure the builder is in a valid state when
- * ilo_builder_end() is called.
- */
-bool
-ilo_builder_validate(struct ilo_builder *builder,
- unsigned bo_count, struct intel_bo **bos)
-{
- const unsigned max_bo_count = 2;
- struct intel_bo *bos_to_submit[ILO_BUILDER_WRITER_COUNT + max_bo_count];
- int i;
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++)
- bos_to_submit[i] = builder->writers[i].bo;
-
- if (bo_count) {
- assert(bo_count <= max_bo_count);
- if (bo_count > max_bo_count)
- return false;
-
- memcpy(&bos_to_submit[ILO_BUILDER_WRITER_COUNT],
- bos, sizeof(*bos) * bo_count);
- i += bo_count;
- }
-
- return intel_winsys_can_submit_bo(builder->winsys, bos_to_submit, i);
-}
-
-/**
- * Take a snapshot of the writer state.
- */
-void
-ilo_builder_batch_snapshot(const struct ilo_builder *builder,
- struct ilo_builder_snapshot *snapshot)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const struct ilo_builder_writer *writer = &builder->writers[which];
-
- snapshot->reloc_count = intel_bo_get_reloc_count(writer->bo);
- snapshot->used = writer->used;
- snapshot->stolen = writer->stolen;
- snapshot->item_used = writer->item_used;
-}
-
-/**
- * Restore the writer state to when the snapshot was taken, except that it
- * does not (unnecessarily) shrink BOs or the item array.
- */
-void
-ilo_builder_batch_restore(struct ilo_builder *builder,
- const struct ilo_builder_snapshot *snapshot)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- intel_bo_truncate_relocs(writer->bo, snapshot->reloc_count);
- writer->used = snapshot->used;
- writer->stolen = snapshot->stolen;
- writer->item_used = snapshot->item_used;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_builder.h b/src/gallium/drivers/ilo/core/ilo_builder.h
deleted file mode 100644
index 6e26f22aff1..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_builder.h
+++ /dev/null
@@ -1,557 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_H
-#define ILO_BUILDER_H
-
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_debug.h"
-#include "ilo_dev.h"
-
-enum ilo_builder_writer_type {
- ILO_BUILDER_WRITER_BATCH,
- ILO_BUILDER_WRITER_INSTRUCTION,
-
- ILO_BUILDER_WRITER_COUNT,
-};
-
-enum ilo_builder_item_type {
- /* for dynamic buffer */
- ILO_BUILDER_ITEM_BLOB,
- ILO_BUILDER_ITEM_CLIP_VIEWPORT,
- ILO_BUILDER_ITEM_SF_VIEWPORT,
- ILO_BUILDER_ITEM_SCISSOR_RECT,
- ILO_BUILDER_ITEM_CC_VIEWPORT,
- ILO_BUILDER_ITEM_COLOR_CALC,
- ILO_BUILDER_ITEM_DEPTH_STENCIL,
- ILO_BUILDER_ITEM_BLEND,
- ILO_BUILDER_ITEM_SAMPLER,
- ILO_BUILDER_ITEM_INTERFACE_DESCRIPTOR,
-
- /* for surface buffer */
- ILO_BUILDER_ITEM_SURFACE,
- ILO_BUILDER_ITEM_BINDING_TABLE,
-
- /* for instruction buffer */
- ILO_BUILDER_ITEM_KERNEL,
-
- ILO_BUILDER_ITEM_COUNT,
-};
-
-struct ilo_builder_item {
- enum ilo_builder_item_type type;
- unsigned offset;
- unsigned size;
-};
-
-struct ilo_builder_writer {
- /* internal flags */
- unsigned flags;
-
- unsigned size;
- struct intel_bo *bo;
- void *ptr;
-
- /* data written to the bottom */
- unsigned used;
- /* data written to the top */
- unsigned stolen;
-
- /* for decoding */
- struct ilo_builder_item *items;
- unsigned item_alloc;
- unsigned item_used;
-};
-
-/**
- * A snapshot of the writer state.
- */
-struct ilo_builder_snapshot {
- unsigned reloc_count;
-
- unsigned used;
- unsigned stolen;
- unsigned item_used;
-};
-
-struct ilo_builder {
- const struct ilo_dev *dev;
- struct intel_winsys *winsys;
- uint32_t mocs;
-
- struct ilo_builder_writer writers[ILO_BUILDER_WRITER_COUNT];
- bool unrecoverable_error;
-
- /* for writers that have their data appended */
- unsigned begin_used[ILO_BUILDER_WRITER_COUNT];
-
- /* for STATE_BASE_ADDRESS */
- unsigned sba_instruction_pos;
-};
-
-void
-ilo_builder_init(struct ilo_builder *builder,
- const struct ilo_dev *dev,
- struct intel_winsys *winsys);
-
-void
-ilo_builder_reset(struct ilo_builder *builder);
-
-void
-ilo_builder_decode(struct ilo_builder *builder);
-
-bool
-ilo_builder_begin(struct ilo_builder *builder);
-
-struct intel_bo *
-ilo_builder_end(struct ilo_builder *builder, unsigned *used);
-
-bool
-ilo_builder_validate(struct ilo_builder *builder,
- unsigned bo_count, struct intel_bo **bos);
-
-/**
- * Return true if the builder has a relocation entry for \p bo.
- */
-static inline bool
-ilo_builder_has_reloc(const struct ilo_builder *builder,
- struct intel_bo *bo)
-{
- int i;
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++) {
- const struct ilo_builder_writer *writer = &builder->writers[i];
- if (intel_bo_has_reloc(writer->bo, bo))
- return true;
- }
-
- return false;
-}
-
-void
-ilo_builder_writer_discard(struct ilo_builder *builder,
- enum ilo_builder_writer_type which);
-
-bool
-ilo_builder_writer_grow(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned new_size, bool preserve);
-
-bool
-ilo_builder_writer_record(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- enum ilo_builder_item_type type,
- unsigned offset, unsigned size);
-
-static inline void
-ilo_builder_writer_checked_record(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- enum ilo_builder_item_type item,
- unsigned offset, unsigned size)
-{
- if (unlikely(ilo_debug & (ILO_DEBUG_BATCH | ILO_DEBUG_HANG))) {
- if (!ilo_builder_writer_record(builder, which, item, offset, size)) {
- builder->unrecoverable_error = true;
- builder->writers[which].item_used = 0;
- }
- }
-}
-
-/**
- * Return an offset to a region that is aligned to \p alignment and has at
- * least \p size bytes. The region is reserved from the bottom.
- */
-static inline unsigned
-ilo_builder_writer_reserve_bottom(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned alignment, unsigned size)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- unsigned offset;
-
- assert(alignment && util_is_power_of_two(alignment));
- offset = align(writer->used, alignment);
-
- if (unlikely(offset + size > writer->size - writer->stolen)) {
- if (!ilo_builder_writer_grow(builder, which,
- offset + size + writer->stolen, true)) {
- builder->unrecoverable_error = true;
- ilo_builder_writer_discard(builder, which);
- offset = 0;
- }
-
- assert(offset + size <= writer->size - writer->stolen);
- }
-
- return offset;
-}
-
-/**
- * Similar to ilo_builder_writer_reserve_bottom(), but reserve from the top.
- */
-static inline unsigned
-ilo_builder_writer_reserve_top(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned alignment, unsigned size)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- unsigned offset;
-
- assert(alignment && util_is_power_of_two(alignment));
- offset = (writer->size - writer->stolen - size) & ~(alignment - 1);
-
- if (unlikely(offset < writer->used ||
- size > writer->size - writer->stolen)) {
- if (!ilo_builder_writer_grow(builder, which,
- align(writer->used, alignment) + size + writer->stolen, true)) {
- builder->unrecoverable_error = true;
- ilo_builder_writer_discard(builder, which);
- }
-
- offset = (writer->size - writer->stolen - size) & ~(alignment - 1);
- assert(offset + size <= writer->size - writer->stolen);
- }
-
- return offset;
-}
-
-/**
- * Add a relocation entry to the writer.
- */
-static inline void
-ilo_builder_writer_reloc(struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned offset, struct intel_bo *bo,
- unsigned bo_offset, unsigned reloc_flags,
- bool write_presumed_offset_hi)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- uint64_t presumed_offset;
- int err;
-
- if (write_presumed_offset_hi)
- ILO_DEV_ASSERT(builder->dev, 8, 8);
- else
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- assert(offset + sizeof(uint32_t) <= writer->used ||
- (offset >= writer->size - writer->stolen &&
- offset + sizeof(uint32_t) <= writer->size));
-
- err = intel_bo_add_reloc(writer->bo, offset, bo, bo_offset,
- reloc_flags, &presumed_offset);
- if (unlikely(err))
- builder->unrecoverable_error = true;
-
- if (write_presumed_offset_hi) {
- *((uint64_t *) ((char *) writer->ptr + offset)) = presumed_offset;
- } else {
- /* 32-bit addressing */
- assert(presumed_offset == (uint64_t) ((uint32_t) presumed_offset));
- *((uint32_t *) ((char *) writer->ptr + offset)) = presumed_offset;
- }
-}
-
-/**
- * Reserve a region from the dynamic buffer. Both the offset, in bytes, and
- * the pointer to the reserved region are returned. The pointer is only valid
- * until the next reserve call.
- *
- * Note that \p alignment is in bytes and \p len is in DWords.
- */
-static inline uint32_t
-ilo_builder_dynamic_pointer(struct ilo_builder *builder,
- enum ilo_builder_item_type item,
- unsigned alignment, unsigned len,
- uint32_t **dw)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const unsigned size = len << 2;
- const unsigned offset = ilo_builder_writer_reserve_top(builder,
- which, alignment, size);
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- /* all states are at least aligned to 32-bytes */
- if (item != ILO_BUILDER_ITEM_BLOB)
- assert(alignment % 32 == 0);
-
- *dw = (uint32_t *) ((char *) writer->ptr + offset);
-
- writer->stolen = writer->size - offset;
-
- ilo_builder_writer_checked_record(builder, which, item, offset, size);
-
- return offset;
-}
-
-/**
- * Write a dynamic state to the dynamic buffer.
- */
-static inline uint32_t
-ilo_builder_dynamic_write(struct ilo_builder *builder,
- enum ilo_builder_item_type item,
- unsigned alignment, unsigned len,
- const uint32_t *dw)
-{
- uint32_t offset, *dst;
-
- offset = ilo_builder_dynamic_pointer(builder, item, alignment, len, &dst);
- memcpy(dst, dw, len << 2);
-
- return offset;
-}
-
-/**
- * Reserve some space from the top (for prefetches).
- */
-static inline void
-ilo_builder_dynamic_pad_top(struct ilo_builder *builder, unsigned len)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const unsigned size = len << 2;
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- if (writer->stolen < size) {
- ilo_builder_writer_reserve_top(builder, which,
- 1, size - writer->stolen);
- writer->stolen = size;
- }
-}
-
-static inline unsigned
-ilo_builder_dynamic_used(const struct ilo_builder *builder)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const struct ilo_builder_writer *writer = &builder->writers[which];
-
- return writer->stolen >> 2;
-}
-
-/**
- * Reserve a region from the surface buffer. Both the offset, in bytes, and
- * the pointer to the reserved region are returned. The pointer is only valid
- * until the next reserve call.
- *
- * Note that \p alignment is in bytes and \p len is in DWords.
- */
-static inline uint32_t
-ilo_builder_surface_pointer(struct ilo_builder *builder,
- enum ilo_builder_item_type item,
- unsigned alignment, unsigned len,
- uint32_t **dw)
-{
- assert(item == ILO_BUILDER_ITEM_SURFACE ||
- item == ILO_BUILDER_ITEM_BINDING_TABLE);
-
- return ilo_builder_dynamic_pointer(builder, item, alignment, len, dw);
-}
-
-/**
- * Add a relocation entry for a DWord of a surface state.
- */
-static inline void
-ilo_builder_surface_reloc(struct ilo_builder *builder,
- uint32_t offset, unsigned dw_index,
- struct intel_bo *bo, unsigned bo_offset,
- unsigned reloc_flags)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
-
- ilo_builder_writer_reloc(builder, which, offset + (dw_index << 2),
- bo, bo_offset, reloc_flags, false);
-}
-
-static inline void
-ilo_builder_surface_reloc64(struct ilo_builder *builder,
- uint32_t offset, unsigned dw_index,
- struct intel_bo *bo, unsigned bo_offset,
- unsigned reloc_flags)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
-
- ilo_builder_writer_reloc(builder, which, offset + (dw_index << 2),
- bo, bo_offset, reloc_flags, true);
-}
-
-static inline unsigned
-ilo_builder_surface_used(const struct ilo_builder *builder)
-{
- return ilo_builder_dynamic_used(builder);
-}
-
-/**
- * Write a kernel to the instruction buffer. The offset, in bytes, of the
- * kernel is returned.
- */
-static inline uint32_t
-ilo_builder_instruction_write(struct ilo_builder *builder,
- unsigned size, const void *kernel)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_INSTRUCTION;
- /*
- * From the Sandy Bridge PRM, volume 4 part 2, page 112:
- *
- * "Due to prefetch of the instruction stream, the EUs may attempt to
- * access up to 8 instructions (128 bytes) beyond the end of the
- * kernel program - possibly into the next memory page. Although
- * these instructions will not be executed, software must account for
- * the prefetch in order to avoid invalid page access faults."
- */
- const unsigned reserved_size = size + 128;
- /* kernels are aligned to 64 bytes */
- const unsigned alignment = 64;
- const unsigned offset = ilo_builder_writer_reserve_bottom(builder,
- which, alignment, reserved_size);
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- memcpy((char *) writer->ptr + offset, kernel, size);
-
- writer->used = offset + size;
-
- ilo_builder_writer_checked_record(builder, which,
- ILO_BUILDER_ITEM_KERNEL, offset, size);
-
- return offset;
-}
-
-/**
- * Reserve a region from the batch buffer. Both the offset, in DWords, and
- * the pointer to the reserved region are returned. The pointer is only valid
- * until the next reserve call.
- *
- * Note that \p len is in DWords.
- */
-static inline unsigned
-ilo_builder_batch_pointer(struct ilo_builder *builder,
- unsigned len, uint32_t **dw)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- /*
- * We know the batch bo is always aligned. Using 1 here should allow the
- * compiler to optimize away aligning.
- */
- const unsigned alignment = 1;
- const unsigned size = len << 2;
- const unsigned offset = ilo_builder_writer_reserve_bottom(builder,
- which, alignment, size);
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- assert(offset % 4 == 0);
- *dw = (uint32_t *) ((char *) writer->ptr + offset);
-
- writer->used = offset + size;
-
- return offset >> 2;
-}
-
-/**
- * Write a command to the batch buffer.
- */
-static inline unsigned
-ilo_builder_batch_write(struct ilo_builder *builder,
- unsigned len, const uint32_t *dw)
-{
- unsigned pos;
- uint32_t *dst;
-
- pos = ilo_builder_batch_pointer(builder, len, &dst);
- memcpy(dst, dw, len << 2);
-
- return pos;
-}
-
-/**
- * Add a relocation entry for a DWord of a command.
- */
-static inline void
-ilo_builder_batch_reloc(struct ilo_builder *builder, unsigned pos,
- struct intel_bo *bo, unsigned bo_offset,
- unsigned reloc_flags)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
-
- ilo_builder_writer_reloc(builder, which, pos << 2,
- bo, bo_offset, reloc_flags, false);
-}
-
-static inline void
-ilo_builder_batch_reloc64(struct ilo_builder *builder, unsigned pos,
- struct intel_bo *bo, unsigned bo_offset,
- unsigned reloc_flags)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
-
- ilo_builder_writer_reloc(builder, which, pos << 2,
- bo, bo_offset, reloc_flags, true);
-}
-
-static inline unsigned
-ilo_builder_batch_used(const struct ilo_builder *builder)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const struct ilo_builder_writer *writer = &builder->writers[which];
-
- return writer->used >> 2;
-}
-
-static inline unsigned
-ilo_builder_batch_space(const struct ilo_builder *builder)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const struct ilo_builder_writer *writer = &builder->writers[which];
-
- return (writer->size - writer->stolen - writer->used) >> 2;
-}
-
-static inline void
-ilo_builder_batch_discard(struct ilo_builder *builder)
-{
- ilo_builder_writer_discard(builder, ILO_BUILDER_WRITER_BATCH);
-}
-
-static inline void
-ilo_builder_batch_print_stats(const struct ilo_builder *builder)
-{
- const enum ilo_builder_writer_type which = ILO_BUILDER_WRITER_BATCH;
- const struct ilo_builder_writer *writer = &builder->writers[which];
-
- ilo_printf("%d+%d bytes (%d%% full)\n",
- writer->used, writer->stolen,
- (writer->used + writer->stolen) * 100 / writer->size);
-}
-
-void
-ilo_builder_batch_snapshot(const struct ilo_builder *builder,
- struct ilo_builder_snapshot *snapshot);
-
-void
-ilo_builder_batch_restore(struct ilo_builder *builder,
- const struct ilo_builder_snapshot *snapshot);
-
-#endif /* ILO_BUILDER_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_3d.h b/src/gallium/drivers/ilo/core/ilo_builder_3d.h
deleted file mode 100644
index fb8b53cbe23..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_builder_3d.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_3D_H
-#define ILO_BUILDER_3D_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_builder_3d_top.h"
-#include "ilo_builder_3d_bottom.h"
-
-struct gen6_3dprimitive_info {
- enum gen_3dprim_type topology;
- bool indexed;
-
- uint32_t vertex_count;
- uint32_t vertex_start;
- uint32_t instance_count;
- uint32_t instance_start;
- int32_t vertex_base;
-};
-
-static inline void
-gen6_3DPRIMITIVE(struct ilo_builder *builder,
- const struct gen6_3dprimitive_info *info)
-{
- const uint8_t cmd_len = 6;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) | (cmd_len - 2) |
- info->topology << GEN6_3DPRIM_DW0_TYPE__SHIFT;
- if (info->indexed)
- dw[0] |= GEN6_3DPRIM_DW0_ACCESS_RANDOM;
-
- dw[1] = info->vertex_count;
- dw[2] = info->vertex_start;
- dw[3] = info->instance_count;
- dw[4] = info->instance_start;
- dw[5] = info->vertex_base;
-}
-
-static inline void
-gen7_3DPRIMITIVE(struct ilo_builder *builder,
- const struct gen6_3dprimitive_info *info)
-{
- const uint8_t cmd_len = 7;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) | (cmd_len - 2);
-
- dw[1] = info->topology << GEN7_3DPRIM_DW1_TYPE__SHIFT;
- if (info->indexed)
- dw[1] |= GEN7_3DPRIM_DW1_ACCESS_RANDOM;
-
- dw[2] = info->vertex_count;
- dw[3] = info->vertex_start;
- dw[4] = info->instance_count;
- dw[5] = info->instance_start;
- dw[6] = info->vertex_base;
-}
-
-#endif /* ILO_BUILDER_3D_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_3d_bottom.h b/src/gallium/drivers/ilo/core/ilo_builder_3d_bottom.h
deleted file mode 100644
index 2e9470e66e9..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_builder_3d_bottom.h
+++ /dev/null
@@ -1,1118 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_3D_BOTTOM_H
-#define ILO_BUILDER_3D_BOTTOM_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_state_cc.h"
-#include "ilo_state_raster.h"
-#include "ilo_state_sbe.h"
-#include "ilo_state_shader.h"
-#include "ilo_state_viewport.h"
-#include "ilo_state_zs.h"
-#include "ilo_vma.h"
-#include "ilo_builder.h"
-#include "ilo_builder_3d_top.h"
-
-static inline void
-gen6_3DSTATE_CLIP(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CLIP) | (cmd_len - 2);
- /* see raster_set_gen6_3DSTATE_CLIP() */
- dw[1] = rs->clip[0];
- dw[2] = rs->clip[1];
- dw[3] = rs->clip[2];
-}
-
-static inline void
-gen6_3DSTATE_SF(struct ilo_builder *builder,
- const struct ilo_state_raster *rs,
- const struct ilo_state_sbe *sbe)
-{
- const uint8_t cmd_len = 20;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
- /* see sbe_set_gen8_3DSTATE_SBE() */
- dw[1] = sbe->sbe[0];
-
- /* see raster_set_gen7_3DSTATE_SF() */
- dw[2] = rs->sf[0];
- dw[3] = rs->sf[1];
- dw[4] = rs->sf[2];
- dw[5] = rs->raster[1];
- dw[6] = rs->raster[2];
- dw[7] = rs->raster[3];
-
- /* see sbe_set_gen8_3DSTATE_SBE_SWIZ() */
- memcpy(&dw[8], sbe->swiz, sizeof(*dw) * 8);
-
- dw[16] = sbe->sbe[1];
- dw[17] = sbe->sbe[2];
- /* WrapShortest enables */
- dw[18] = 0;
- dw[19] = 0;
-}
-
-static inline void
-gen7_3DSTATE_SF(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 4 : 7;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
-
- /* see raster_set_gen7_3DSTATE_SF() or raster_set_gen8_3DSTATE_SF() */
- dw[1] = rs->sf[0];
- dw[2] = rs->sf[1];
- dw[3] = rs->sf[2];
- if (ilo_dev_gen(builder->dev) < ILO_GEN(8)) {
- dw[4] = rs->raster[1];
- dw[5] = rs->raster[2];
- dw[6] = rs->raster[3];
- }
-}
-
-static inline void
-gen7_3DSTATE_SBE(struct ilo_builder *builder,
- const struct ilo_state_sbe *sbe)
-{
- const uint8_t cmd_len = 14;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SBE) | (cmd_len - 2);
- /* see sbe_set_gen8_3DSTATE_SBE() and sbe_set_gen8_3DSTATE_SBE_SWIZ() */
- dw[1] = sbe->sbe[0];
- memcpy(&dw[2], sbe->swiz, sizeof(*dw) * 8);
- dw[10] = sbe->sbe[1];
- dw[11] = sbe->sbe[2];
-
- /* WrapShortest enables */
- dw[12] = 0;
- dw[13] = 0;
-}
-
-static inline void
-gen8_3DSTATE_SBE(struct ilo_builder *builder,
- const struct ilo_state_sbe *sbe)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- /* see sbe_set_gen8_3DSTATE_SBE() */
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SBE) | (cmd_len - 2);
- dw[1] = sbe->sbe[0];
- dw[2] = sbe->sbe[1];
- dw[3] = sbe->sbe[2];
-}
-
-static inline void
-gen8_3DSTATE_SBE_SWIZ(struct ilo_builder *builder,
- const struct ilo_state_sbe *sbe)
-{
- const uint8_t cmd_len = 11;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_SBE_SWIZ) | (cmd_len - 2);
- /* see sbe_set_gen8_3DSTATE_SBE_SWIZ() */
- memcpy(&dw[1], sbe->swiz, sizeof(*dw) * 8);
- /* WrapShortest enables */
- dw[9] = 0;
- dw[10] = 0;
-}
-
-static inline void
-gen8_3DSTATE_RASTER(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 5;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_RASTER) | (cmd_len - 2);
- /* see raster_set_gen8_3DSTATE_RASTER() */
- dw[1] = rs->raster[0];
- dw[2] = rs->raster[1];
- dw[3] = rs->raster[2];
- dw[4] = rs->raster[3];
-}
-
-static inline void
-gen6_3DSTATE_WM(struct ilo_builder *builder,
- const struct ilo_state_raster *rs,
- const struct ilo_state_ps *ps,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 9;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
- dw[1] = kernel_offset;
- /* see raster_set_gen6_3dstate_wm() and ps_set_gen6_3dstate_wm() */
- dw[2] = ps->ps[0];
- dw[3] = ps->ps[1];
- dw[4] = rs->wm[0] | ps->ps[2];
- dw[5] = rs->wm[1] | ps->ps[3];
- dw[6] = rs->wm[2] | ps->ps[4];
- dw[7] = 0; /* kernel 1 */
- dw[8] = 0; /* kernel 2 */
-
- if (ilo_state_ps_get_scratch_size(ps)) {
- ilo_builder_batch_reloc(builder, pos + 2, scratch_bo,
- ps->ps[0], 0);
- }
-}
-
-static inline void
-gen7_3DSTATE_WM(struct ilo_builder *builder,
- const struct ilo_state_raster *rs,
- const struct ilo_state_ps *ps)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
- /* see raster_set_gen8_3DSTATE_WM() and ps_set_gen7_3dstate_wm() */
- dw[1] = rs->wm[0] | ps->ps[0];
- dw[2] = ps->ps[1];
-}
-
-static inline void
-gen8_3DSTATE_WM(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
- /* see raster_set_gen8_3DSTATE_WM() */
- dw[1] = rs->wm[0];
-}
-
-static inline void
-gen8_3DSTATE_WM_DEPTH_STENCIL(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_WM_DEPTH_STENCIL) | (cmd_len - 2);
- /* see cc_set_gen8_3DSTATE_WM_DEPTH_STENCIL() */
- dw[1] = cc->ds[0];
- dw[2] = cc->ds[1];
-}
-
-static inline void
-gen8_3DSTATE_WM_HZ_OP(struct ilo_builder *builder,
- const struct ilo_state_raster *rs,
- uint16_t width, uint16_t height)
-{
- const uint8_t cmd_len = 5;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_WM_HZ_OP) | (cmd_len - 2);
- /* see raster_set_gen8_3dstate_wm_hz_op() */
- dw[1] = rs->wm[1];
- dw[2] = 0;
- /* exclusive */
- dw[3] = height << 16 | width;
- dw[4] = rs->wm[2];
-}
-
-static inline void
-gen8_disable_3DSTATE_WM_HZ_OP(struct ilo_builder *builder)
-{
- const uint8_t cmd_len = 5;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_WM_HZ_OP) | (cmd_len - 2);
- dw[1] = 0;
- dw[2] = 0;
- dw[3] = 0;
- dw[4] = 0;
-}
-
-static inline void
-gen8_3DSTATE_WM_CHROMAKEY(struct ilo_builder *builder)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_WM_CHROMAKEY) | (cmd_len - 2);
- dw[1] = 0;
-}
-
-static inline void
-gen7_3DSTATE_PS(struct ilo_builder *builder,
- const struct ilo_state_ps *ps,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 8;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- /* see ps_set_gen7_3DSTATE_PS() */
- dw[2] = ps->ps[2];
- dw[3] = ps->ps[3];
- dw[4] = ps->ps[4];
- dw[5] = ps->ps[5];
- dw[6] = 0; /* kernel 1 */
- dw[7] = 0; /* kernel 2 */
-
- if (ilo_state_ps_get_scratch_size(ps)) {
- ilo_builder_batch_reloc(builder, pos + 3, scratch_bo,
- ps->ps[3], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_PS(struct ilo_builder *builder,
- const struct ilo_state_ps *ps,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 12;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- dw[2] = 0;
- /* see ps_set_gen8_3DSTATE_PS() */
- dw[3] = ps->ps[0];
- dw[4] = ps->ps[1];
- dw[5] = 0;
- dw[6] = ps->ps[2];
- dw[7] = ps->ps[3];
- dw[8] = 0; /* kernel 1 */
- dw[9] = 0;
- dw[10] = 0; /* kernel 2 */
- dw[11] = 0;
-
- if (ilo_state_ps_get_scratch_size(ps)) {
- ilo_builder_batch_reloc64(builder, pos + 4, scratch_bo,
- ps->ps[1], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_PS_EXTRA(struct ilo_builder *builder,
- const struct ilo_state_ps *ps)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_PS_EXTRA) | (cmd_len - 2);
- /* see ps_set_gen8_3DSTATE_PS_EXTRA() */
- dw[1] = ps->ps[4];
-}
-
-static inline void
-gen8_3DSTATE_PS_BLEND(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_PS_BLEND) | (cmd_len - 2);
- /* see cc_set_gen8_3DSTATE_PS_BLEND() */
- dw[1] = cc->blend[0];
-}
-
-static inline void
-gen6_3DSTATE_CONSTANT_PS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen6_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3DSTATE_CONSTANT_PS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen7_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(struct ilo_builder *builder,
- uint32_t binding_table)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS,
- binding_table);
-}
-
-static inline void
-gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(struct ilo_builder *builder,
- uint32_t sampler_state)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS,
- sampler_state);
-}
-
-static inline void
-gen6_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
- const struct ilo_state_raster *rs,
- const struct ilo_state_sample_pattern *pattern,
- uint8_t sample_count)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 4 : 3;
- const uint32_t *packed = (const uint32_t *)
- ilo_state_sample_pattern_get_packed_offsets(pattern,
- builder->dev, sample_count);
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) | (cmd_len - 2);
- /* see raster_set_gen8_3DSTATE_MULTISAMPLE() */
- dw[1] = rs->sample[0];
-
- /* see sample_pattern_set_gen8_3DSTATE_SAMPLE_PATTERN() */
- dw[2] = (sample_count >= 4) ? packed[0] : 0;
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
- dw[3] = (sample_count >= 8) ? packed[1] : 0;
-}
-
-static inline void
-gen8_3DSTATE_MULTISAMPLE(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) | (cmd_len - 2);
- /* see raster_set_gen8_3DSTATE_MULTISAMPLE() */
- dw[1] = rs->sample[0];
-}
-
-static inline void
-gen8_3DSTATE_SAMPLE_PATTERN(struct ilo_builder *builder,
- const struct ilo_state_sample_pattern *pattern)
-{
- const uint8_t cmd_len = 9;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_SAMPLE_PATTERN) | (cmd_len - 2);
- dw[1] = 0;
- dw[2] = 0;
- dw[3] = 0;
- dw[4] = 0;
- /* see sample_pattern_set_gen8_3DSTATE_SAMPLE_PATTERN() */
- dw[5] = ((const uint32_t *) pattern->pattern_8x)[1];
- dw[6] = ((const uint32_t *) pattern->pattern_8x)[0];
- dw[7] = ((const uint32_t *) pattern->pattern_4x)[0];
- dw[8] = pattern->pattern_1x[0] << 16 |
- ((const uint16_t *) pattern->pattern_2x)[0];
-}
-
-static inline void
-gen6_3DSTATE_SAMPLE_MASK(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK) | (cmd_len - 2);
- /* see raster_set_gen6_3DSTATE_SAMPLE_MASK() */
- dw[1] = rs->sample[1];
-}
-
-static inline void
-gen6_3DSTATE_DRAWING_RECTANGLE(struct ilo_builder *builder,
- unsigned x, unsigned y,
- unsigned width, unsigned height)
-{
- const uint8_t cmd_len = 4;
- unsigned xmax = x + width - 1;
- unsigned ymax = y + height - 1;
- unsigned rect_limit;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) {
- rect_limit = 16383;
- }
- else {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 230:
- *
- * "[DevSNB] Errata: This field (Clipped Drawing Rectangle Y Min)
- * must be an even number"
- */
- assert(y % 2 == 0);
-
- rect_limit = 8191;
- }
-
- if (x > rect_limit) x = rect_limit;
- if (y > rect_limit) y = rect_limit;
- if (xmax > rect_limit) xmax = rect_limit;
- if (ymax > rect_limit) ymax = rect_limit;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_DRAWING_RECTANGLE) | (cmd_len - 2);
- dw[1] = y << 16 | x;
- dw[2] = ymax << 16 | xmax;
- /*
- * There is no need to set the origin. It is intended to support front
- * buffer rendering.
- */
- dw[3] = 0;
-}
-
-static inline void
-gen6_3DSTATE_POLY_STIPPLE_OFFSET(struct ilo_builder *builder,
- const struct ilo_state_poly_stipple *stipple)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_OFFSET) | (cmd_len - 2);
- /* constant */
- dw[1] = 0;
-}
-
-static inline void
-gen6_3DSTATE_POLY_STIPPLE_PATTERN(struct ilo_builder *builder,
- const struct ilo_state_poly_stipple *stipple)
-{
- const uint8_t cmd_len = 33;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_PATTERN) | (cmd_len - 2);
- /* see poly_stipple_set_gen6_3DSTATE_POLY_STIPPLE_PATTERN() */
- memcpy(&dw[1], stipple->stipple, sizeof(stipple->stipple));
-}
-
-static inline void
-gen6_3DSTATE_LINE_STIPPLE(struct ilo_builder *builder,
- const struct ilo_state_line_stipple *stipple)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_LINE_STIPPLE) | (cmd_len - 2);
- /* see line_stipple_set_gen6_3DSTATE_LINE_STIPPLE() */
- dw[1] = stipple->stipple[0];
- dw[2] = stipple->stipple[1];
-}
-
-static inline void
-gen6_3DSTATE_AA_LINE_PARAMETERS(struct ilo_builder *builder,
- const struct ilo_state_raster *rs)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_AA_LINE_PARAMETERS) | (cmd_len - 2);
- /* constant */
- dw[1] = 0 << GEN6_AA_LINE_DW1_BIAS__SHIFT |
- 0 << GEN6_AA_LINE_DW1_SLOPE__SHIFT;
- dw[2] = 0 << GEN6_AA_LINE_DW2_CAP_BIAS__SHIFT |
- 0 << GEN6_AA_LINE_DW2_CAP_SLOPE__SHIFT;
-}
-
-static inline void
-gen6_3DSTATE_DEPTH_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_zs *zs)
-{
- const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
- GEN7_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER) :
- GEN6_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER);
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 8 : 7;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2);
-
- /*
- * see zs_set_gen6_3DSTATE_DEPTH_BUFFER() and
- * zs_set_gen7_3DSTATE_DEPTH_BUFFER()
- */
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[1] = zs->depth[0];
- dw[2] = 0;
- dw[3] = 0;
- dw[4] = zs->depth[2];
- dw[5] = zs->depth[3];
- dw[6] = 0;
- dw[7] = zs->depth[4];
-
- dw[5] |= builder->mocs << GEN8_DEPTH_DW5_MOCS__SHIFT;
-
- if (zs->z_vma) {
- ilo_builder_batch_reloc64(builder, pos + 2, zs->z_vma->bo,
- zs->z_vma->bo_offset + zs->depth[1],
- (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- } else {
- dw[1] = zs->depth[0];
- dw[2] = 0;
- dw[3] = zs->depth[2];
- dw[4] = zs->depth[3];
- dw[5] = 0;
- dw[6] = zs->depth[4];
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
- dw[4] |= builder->mocs << GEN7_DEPTH_DW4_MOCS__SHIFT;
- else
- dw[6] |= builder->mocs << GEN6_DEPTH_DW6_MOCS__SHIFT;
-
- if (zs->z_vma) {
- ilo_builder_batch_reloc(builder, pos + 2, zs->z_vma->bo,
- zs->z_vma->bo_offset + zs->depth[1],
- (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- }
-}
-
-static inline void
-gen6_3DSTATE_STENCIL_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_zs *zs)
-{
- const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
- GEN7_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER) :
- GEN6_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER);
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 5 : 3;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2);
-
- /* see zs_set_gen6_3DSTATE_STENCIL_BUFFER() */
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[1] = zs->stencil[0];
- dw[2] = 0;
- dw[3] = 0;
- dw[4] = zs->stencil[2];
-
- dw[1] |= builder->mocs << GEN8_STENCIL_DW1_MOCS__SHIFT;
-
- if (zs->s_vma) {
- ilo_builder_batch_reloc64(builder, pos + 2, zs->s_vma->bo,
- zs->s_vma->bo_offset + zs->stencil[1],
- (zs->s_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- } else {
- dw[1] = zs->stencil[0];
- dw[2] = 0;
-
- dw[1] |= builder->mocs << GEN6_STENCIL_DW1_MOCS__SHIFT;
-
- if (zs->s_vma) {
- ilo_builder_batch_reloc(builder, pos + 2, zs->s_vma->bo,
- zs->s_vma->bo_offset + zs->stencil[1],
- (zs->s_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- }
-}
-
-static inline void
-gen6_3DSTATE_HIER_DEPTH_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_zs *zs)
-{
- const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
- GEN7_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER) :
- GEN6_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER);
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 5 : 3;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2);
-
- /* see zs_set_gen6_3DSTATE_HIER_DEPTH_BUFFER() */
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[1] = zs->hiz[0];
- dw[2] = 0;
- dw[3] = 0;
- dw[4] = zs->hiz[2];
-
- dw[1] |= builder->mocs << GEN8_HIZ_DW1_MOCS__SHIFT;
-
- if (zs->hiz_vma) {
- ilo_builder_batch_reloc64(builder, pos + 2, zs->hiz_vma->bo,
- zs->hiz_vma->bo_offset + zs->hiz[1],
- (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- } else {
- dw[1] = zs->hiz[0];
- dw[2] = 0;
-
- dw[1] |= builder->mocs << GEN6_HIZ_DW1_MOCS__SHIFT;
-
- if (zs->hiz_vma) {
- ilo_builder_batch_reloc(builder, pos + 2, zs->hiz_vma->bo,
- zs->hiz_vma->bo_offset + zs->hiz[1],
- (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- }
-}
-
-static inline void
-gen6_3DSTATE_CLEAR_PARAMS(struct ilo_builder *builder,
- uint32_t clear_val)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) |
- GEN6_CLEAR_PARAMS_DW0_VALID |
- (cmd_len - 2);
- dw[1] = clear_val;
-}
-
-static inline void
-gen7_3DSTATE_CLEAR_PARAMS(struct ilo_builder *builder,
- uint32_t clear_val)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) | (cmd_len - 2);
- dw[1] = clear_val;
- dw[2] = GEN7_CLEAR_PARAMS_DW2_VALID;
-}
-
-static inline void
-gen6_3DSTATE_VIEWPORT_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t clip_viewport,
- uint32_t sf_viewport,
- uint32_t cc_viewport)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VIEWPORT_STATE_POINTERS) |
- GEN6_VP_PTR_DW0_CLIP_CHANGED |
- GEN6_VP_PTR_DW0_SF_CHANGED |
- GEN6_VP_PTR_DW0_CC_CHANGED |
- (cmd_len - 2);
- dw[1] = clip_viewport;
- dw[2] = sf_viewport;
- dw[3] = cc_viewport;
-}
-
-static inline void
-gen6_3DSTATE_SCISSOR_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t scissor_rect)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SCISSOR_STATE_POINTERS) |
- (cmd_len - 2);
- dw[1] = scissor_rect;
-}
-
-static inline void
-gen6_3DSTATE_CC_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t blend_state,
- uint32_t depth_stencil_state,
- uint32_t color_calc_state)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CC_STATE_POINTERS) | (cmd_len - 2);
- dw[1] = blend_state | GEN6_CC_PTR_DW1_BLEND_CHANGED;
- dw[2] = depth_stencil_state | GEN6_CC_PTR_DW2_ZS_CHANGED;
- dw[3] = color_calc_state | GEN6_CC_PTR_DW3_CC_CHANGED;
-}
-
-static inline void
-gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(struct ilo_builder *builder,
- uint32_t sf_clip_viewport)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
- sf_clip_viewport);
-}
-
-static inline void
-gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(struct ilo_builder *builder,
- uint32_t cc_viewport)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
- cc_viewport);
-}
-
-static inline void
-gen7_3DSTATE_CC_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t color_calc_state)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
- color_calc_state |= 1;
-
- gen7_3dstate_pointer(builder,
- GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, color_calc_state);
-}
-
-static inline void
-gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t depth_stencil_state)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
- depth_stencil_state);
-}
-
-static inline void
-gen7_3DSTATE_BLEND_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t blend_state)
-{
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
- blend_state |= 1;
-
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS,
- blend_state);
-}
-
-static inline uint32_t
-gen6_CLIP_VIEWPORT(struct ilo_builder *builder,
- const struct ilo_state_viewport *vp)
-{
- const int state_align = 32;
- const int state_len = 4 * vp->count;
- uint32_t state_offset, *dw;
- int i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- state_offset = ilo_builder_dynamic_pointer(builder,
- ILO_BUILDER_ITEM_CLIP_VIEWPORT, state_align, state_len, &dw);
-
- for (i = 0; i < vp->count; i++) {
- /* see viewport_matrix_set_gen7_SF_CLIP_VIEWPORT() */
- dw[0] = vp->sf_clip[i][8];
- dw[1] = vp->sf_clip[i][9];
- dw[2] = vp->sf_clip[i][10];
- dw[3] = vp->sf_clip[i][11];
-
- dw += 4;
- }
-
- return state_offset;
-}
-
-static inline uint32_t
-gen6_SF_VIEWPORT(struct ilo_builder *builder,
- const struct ilo_state_viewport *vp)
-{
- const int state_align = 32;
- const int state_len = 8 * vp->count;
- uint32_t state_offset, *dw;
- int i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- state_offset = ilo_builder_dynamic_pointer(builder,
- ILO_BUILDER_ITEM_SF_VIEWPORT, state_align, state_len, &dw);
-
- for (i = 0; i < vp->count; i++) {
- /* see viewport_matrix_set_gen7_SF_CLIP_VIEWPORT() */
- memcpy(dw, vp->sf_clip[i], sizeof(*dw) * 8);
-
- dw += 8;
- }
-
- return state_offset;
-}
-
-static inline uint32_t
-gen7_SF_CLIP_VIEWPORT(struct ilo_builder *builder,
- const struct ilo_state_viewport *vp)
-{
- const int state_align = 64;
- const int state_len = 16 * vp->count;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- /* see viewport_matrix_set_gen7_SF_CLIP_VIEWPORT() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_SF_VIEWPORT,
- state_align, state_len, (const uint32_t *) vp->sf_clip);
-}
-
-static inline uint32_t
-gen6_CC_VIEWPORT(struct ilo_builder *builder,
- const struct ilo_state_viewport *vp)
-{
- const int state_align = 32;
- const int state_len = 2 * vp->count;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /* see viewport_matrix_set_gen6_CC_VIEWPORT() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_CC_VIEWPORT,
- state_align, state_len, (const uint32_t *) vp->cc);
-}
-
-static inline uint32_t
-gen6_SCISSOR_RECT(struct ilo_builder *builder,
- const struct ilo_state_viewport *vp)
-{
- const int state_align = 32;
- const int state_len = 2 * vp->count;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /* see viewport_scissor_set_gen6_SCISSOR_RECT() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_SCISSOR_RECT,
- state_align, state_len, (const uint32_t *) vp->scissor);
-}
-
-static inline uint32_t
-gen6_COLOR_CALC_STATE(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const int state_align = 64;
- const int state_len = 6;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /* see cc_params_set_gen6_COLOR_CALC_STATE() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_COLOR_CALC,
- state_align, state_len, cc->cc);
-}
-
-static inline uint32_t
-gen6_DEPTH_STENCIL_STATE(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const int state_align = 64;
- const int state_len = 3;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- /* see cc_set_gen6_DEPTH_STENCIL_STATE() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_DEPTH_STENCIL,
- state_align, state_len, cc->ds);
-}
-
-static inline uint32_t
-gen6_BLEND_STATE(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const int state_align = 64;
- const int state_len = 2 * cc->blend_state_count;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- if (!state_len)
- return 0;
-
- /* see cc_set_gen6_BLEND_STATE() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_BLEND,
- state_align, state_len, cc->blend);
-}
-
-static inline uint32_t
-gen8_BLEND_STATE(struct ilo_builder *builder,
- const struct ilo_state_cc *cc)
-{
- const int state_align = 64;
- const int state_len = 1 + 2 * cc->blend_state_count;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- /* see cc_set_gen8_BLEND_STATE() */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_BLEND,
- state_align, state_len, &cc->blend[1]);
-}
-
-#endif /* ILO_BUILDER_3D_BOTTOM_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h b/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
deleted file mode 100644
index 3a448719c15..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_builder_3d_top.h
+++ /dev/null
@@ -1,1476 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_3D_TOP_H
-#define ILO_BUILDER_3D_TOP_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_state_sampler.h"
-#include "ilo_state_shader.h"
-#include "ilo_state_sol.h"
-#include "ilo_state_surface.h"
-#include "ilo_state_urb.h"
-#include "ilo_state_vf.h"
-#include "ilo_vma.h"
-#include "ilo_builder.h"
-
-static inline void
-gen6_3DSTATE_URB(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_URB) | (cmd_len - 2);
- /* see urb_set_gen6_3DSTATE_URB() */
- dw[1] = urb->urb[0];
- dw[2] = urb->urb[1];
-}
-
-static inline void
-gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_VS) |
- (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->pcb[0];
-}
-
-static inline void
-gen7_3DSTATE_PUSH_CONSTANT_ALLOC_HS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_HS) |
- (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->pcb[1];
-}
-
-static inline void
-gen7_3DSTATE_PUSH_CONSTANT_ALLOC_DS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_DS) |
- (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->pcb[2];
-}
-
-static inline void
-gen7_3DSTATE_PUSH_CONSTANT_ALLOC_GS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_GS) |
- (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->pcb[3];
-}
-
-static inline void
-gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_PS) |
- (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->pcb[4];
-}
-
-static inline void
-gen7_3DSTATE_URB_VS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_VS) | (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->urb[0];
-}
-
-static inline void
-gen7_3DSTATE_URB_HS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_HS) | (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->urb[1];
-}
-
-static inline void
-gen7_3DSTATE_URB_DS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_DS) | (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->urb[2];
-}
-
-static inline void
-gen7_3DSTATE_URB_GS(struct ilo_builder *builder,
- const struct ilo_state_urb *urb)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_GS) | (cmd_len - 2);
- /* see urb_set_gen7_3dstate_push_constant_alloc() */
- dw[1] = urb->urb[3];
-}
-
-static inline void
-gen75_3DSTATE_VF(struct ilo_builder *builder,
- const struct ilo_state_vf *vf)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7.5, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- /* see vf_params_set_gen75_3DSTATE_VF() */
- dw[0] = GEN75_RENDER_CMD(3D, 3DSTATE_VF) | (cmd_len - 2) |
- vf->cut[0];
- dw[1] = vf->cut[1];
-}
-
-static inline void
-gen6_3DSTATE_VF_STATISTICS(struct ilo_builder *builder,
- bool enable)
-{
- const uint8_t cmd_len = 1;
- const uint32_t dw0 = GEN6_RENDER_CMD(SINGLE_DW, 3DSTATE_VF_STATISTICS) |
- enable;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_write(builder, cmd_len, &dw0);
-}
-
-static inline void
-gen8_3DSTATE_VF_TOPOLOGY(struct ilo_builder *builder,
- enum gen_3dprim_type topology)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_VF_TOPOLOGY) | (cmd_len - 2);
- dw[1] = topology << GEN8_TOPOLOGY_DW1_TYPE__SHIFT;
-}
-
-static inline void
-gen8_3DSTATE_VF_INSTANCING(struct ilo_builder *builder,
- const struct ilo_state_vf *vf,
- uint32_t attr)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_VF_INSTANCING) | (cmd_len - 2);
- dw[1] = attr << GEN8_INSTANCING_DW1_VE_INDEX__SHIFT;
- dw[2] = 0;
- /* see vf_set_gen8_3DSTATE_VF_INSTANCING() */
- if (attr >= vf->internal_ve_count) {
- attr -= vf->internal_ve_count;
-
- dw[1] |= vf->user_instancing[attr][0];
- dw[2] |= vf->user_instancing[attr][1];
- }
-}
-
-static inline void
-gen8_3DSTATE_VF_SGVS(struct ilo_builder *builder,
- const struct ilo_state_vf *vf)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN8_RENDER_CMD(3D, 3DSTATE_VF_SGVS) | (cmd_len - 2);
- /* see vf_params_set_gen8_3DSTATE_VF_SGVS() */
- dw[1] = vf->sgvs[0];
-}
-
-static inline void
-gen6_3DSTATE_VERTEX_BUFFERS(struct ilo_builder *builder,
- const struct ilo_state_vf *vf,
- const struct ilo_state_vertex_buffer *vb,
- unsigned vb_count)
-{
- uint8_t cmd_len;
- uint32_t *dw;
- unsigned pos, i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 82:
- *
- * "From 1 to 33 VBs can be specified..."
- */
- assert(vb_count <= 33);
-
- if (!vb_count)
- return;
-
- cmd_len = 1 + 4 * vb_count;
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_BUFFERS) | (cmd_len - 2);
- dw++;
- pos++;
-
- for (i = 0; i < vb_count; i++) {
- const struct ilo_state_vertex_buffer *b = &vb[i];
-
- /* see vertex_buffer_set_gen8_vertex_buffer_state() */
- dw[0] = b->vb[0] |
- i << GEN6_VB_DW0_INDEX__SHIFT;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
- dw[0] |= builder->mocs << GEN8_VB_DW0_MOCS__SHIFT;
- else
- dw[0] |= builder->mocs << GEN6_VB_DW0_MOCS__SHIFT;
-
- dw[1] = 0;
- dw[2] = 0;
- dw[3] = 0;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- if (b->vma) {
- ilo_builder_batch_reloc64(builder, pos + 1, b->vma->bo,
- b->vma->bo_offset + b->vb[1], 0);
- }
-
- dw[3] |= b->vb[2];
- } else {
- const int8_t elem = vf->vb_to_first_elem[i];
-
- /* see vf_set_gen6_vertex_buffer_state() */
- if (elem >= 0) {
- dw[0] |= vf->user_instancing[elem][0];
- dw[3] |= vf->user_instancing[elem][1];
- }
-
- if (b->vma) {
- ilo_builder_batch_reloc(builder, pos + 1, b->vma->bo,
- b->vma->bo_offset + b->vb[1], 0);
- ilo_builder_batch_reloc(builder, pos + 2, b->vma->bo,
- b->vma->bo_offset + b->vb[2], 0);
- }
- }
-
- dw += 4;
- pos += 4;
- }
-}
-
-/* the user vertex buffer must be uploaded with gen6_user_vertex_buffer() */
-static inline void
-gen6_user_3DSTATE_VERTEX_BUFFERS(struct ilo_builder *builder,
- uint32_t vb_begin, uint32_t vb_end,
- uint32_t stride)
-{
- const struct ilo_builder_writer *bat =
- &builder->writers[ILO_BUILDER_WRITER_BATCH];
- const uint8_t cmd_len = 1 + 4;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_BUFFERS) | (cmd_len - 2);
- dw++;
- pos++;
-
- /* VERTEX_BUFFER_STATE */
- dw[0] = 0 << GEN6_VB_DW0_INDEX__SHIFT |
- GEN6_VB_DW0_ACCESS_VERTEXDATA |
- stride << GEN6_VB_DW0_PITCH__SHIFT;
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
- dw[0] |= GEN7_VB_DW0_ADDR_MODIFIED;
-
- dw[3] = 0;
-
- ilo_builder_batch_reloc(builder, pos + 1, bat->bo, vb_begin, 0);
- ilo_builder_batch_reloc(builder, pos + 2, bat->bo, vb_end, 0);
-}
-
-static inline void
-gen6_3DSTATE_VERTEX_ELEMENTS(struct ilo_builder *builder,
- const struct ilo_state_vf *vf)
-{
- uint8_t cmd_len;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- cmd_len = 1 + 2 * (vf->internal_ve_count + vf->user_ve_count);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_ELEMENTS) | (cmd_len - 2);
- dw++;
-
- /*
- * see vf_params_set_gen6_internal_ve() and
- * vf_set_gen6_3DSTATE_VERTEX_ELEMENTS()
- */
- if (vf->internal_ve_count) {
- memcpy(dw, vf->internal_ve,
- sizeof(vf->internal_ve[0]) * vf->internal_ve_count);
- dw += 2 * vf->internal_ve_count;
- }
-
- memcpy(dw, vf->user_ve, sizeof(vf->user_ve[0]) * vf->user_ve_count);
-}
-
-static inline void
-gen6_3DSTATE_INDEX_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_vf *vf,
- const struct ilo_state_index_buffer *ib)
-{
- const uint8_t cmd_len = 3;
- uint32_t dw0, *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2) |
- builder->mocs << GEN6_IB_DW0_MOCS__SHIFT;
-
- /*
- * see index_buffer_set_gen8_3DSTATE_INDEX_BUFFER() and
- * vf_params_set_gen6_3dstate_index_buffer()
- */
- dw0 |= ib->ib[0];
- if (ilo_dev_gen(builder->dev) <= ILO_GEN(7))
- dw0 |= vf->cut[0];
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = dw0;
- if (ib->vma) {
- ilo_builder_batch_reloc(builder, pos + 1, ib->vma->bo,
- ib->vma->bo_offset + ib->ib[1], 0);
- ilo_builder_batch_reloc(builder, pos + 2, ib->vma->bo,
- ib->vma->bo_offset + ib->ib[2], 0);
- } else {
- dw[1] = 0;
- dw[2] = 0;
- }
-}
-
-static inline void
-gen8_3DSTATE_INDEX_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_vf *vf,
- const struct ilo_state_index_buffer *ib)
-{
- const uint8_t cmd_len = 5;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2);
- /* see index_buffer_set_gen8_3DSTATE_INDEX_BUFFER() */
- dw[1] = ib->ib[0] |
- builder->mocs << GEN8_IB_DW1_MOCS__SHIFT;
-
- if (ib->vma) {
- ilo_builder_batch_reloc64(builder, pos + 2, ib->vma->bo,
- ib->vma->bo_offset + ib->ib[1], 0);
- } else {
- dw[2] = 0;
- dw[3] = 0;
- }
-
- dw[4] = ib->ib[2];
-}
-
-static inline void
-gen6_3DSTATE_VS(struct ilo_builder *builder,
- const struct ilo_state_vs *vs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 6;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- /* see vs_set_gen6_3DSTATE_VS() */
- dw[2] = vs->vs[0];
- dw[3] = vs->vs[1];
- dw[4] = vs->vs[2];
- dw[5] = vs->vs[3];
-
- if (ilo_state_vs_get_scratch_size(vs)) {
- ilo_builder_batch_reloc(builder, pos + 3, scratch_bo,
- vs->vs[1], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_VS(struct ilo_builder *builder,
- const struct ilo_state_vs *vs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 9;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- dw[2] = 0;
- /* see vs_set_gen6_3DSTATE_VS() */
- dw[3] = vs->vs[0];
- dw[4] = vs->vs[1];
- dw[5] = 0;
- dw[6] = vs->vs[2];
- dw[7] = vs->vs[3];
- dw[8] = vs->vs[4];
-
- if (ilo_state_vs_get_scratch_size(vs)) {
- ilo_builder_batch_reloc64(builder, pos + 4, scratch_bo,
- vs->vs[1], 0);
- }
-}
-
-static inline void
-gen7_3DSTATE_HS(struct ilo_builder *builder,
- const struct ilo_state_hs *hs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 7;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_HS) | (cmd_len - 2);
- /* see hs_set_gen7_3DSTATE_HS() */
- dw[1] = hs->hs[0];
- dw[2] = hs->hs[1];
- dw[3] = kernel_offset;
- dw[4] = hs->hs[2];
- dw[5] = hs->hs[3];
- dw[6] = 0;
-
- if (ilo_state_hs_get_scratch_size(hs)) {
- ilo_builder_batch_reloc(builder, pos + 4, scratch_bo,
- hs->hs[2], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_HS(struct ilo_builder *builder,
- const struct ilo_state_hs *hs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 9;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_HS) | (cmd_len - 2);
- /* see hs_set_gen7_3DSTATE_HS() */
- dw[1] = hs->hs[0];
- dw[2] = hs->hs[1];
- dw[3] = kernel_offset;
- dw[4] = 0;
- dw[5] = hs->hs[2];
- dw[6] = 0;
- dw[7] = hs->hs[3];
- dw[8] = 0;
-
- if (ilo_state_hs_get_scratch_size(hs)) {
- ilo_builder_batch_reloc64(builder, pos + 5, scratch_bo,
- hs->hs[2], 0);
- }
-}
-
-static inline void
-gen7_3DSTATE_TE(struct ilo_builder *builder,
- const struct ilo_state_ds *ds)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_TE) | (cmd_len - 2);
- /* see ds_set_gen7_3DSTATE_TE() */
- dw[1] = ds->te[0];
- dw[2] = ds->te[1];
- dw[3] = ds->te[2];
-}
-
-static inline void
-gen7_3DSTATE_DS(struct ilo_builder *builder,
- const struct ilo_state_ds *ds,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 6;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_DS) | (cmd_len - 2);
- /* see ds_set_gen7_3DSTATE_DS() */
- dw[1] = kernel_offset;
- dw[2] = ds->ds[0];
- dw[3] = ds->ds[1];
- dw[4] = ds->ds[2];
- dw[5] = ds->ds[3];
-
- if (ilo_state_ds_get_scratch_size(ds)) {
- ilo_builder_batch_reloc(builder, pos + 3, scratch_bo,
- ds->ds[1], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_DS(struct ilo_builder *builder,
- const struct ilo_state_ds *ds,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 9;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_DS) | (cmd_len - 2);
- /* see ds_set_gen7_3DSTATE_DS() */
- dw[1] = kernel_offset;
- dw[2] = 0;
- dw[3] = ds->ds[0];
- dw[4] = ds->ds[1];
- dw[5] = 0;
- dw[6] = ds->ds[2];
- dw[7] = ds->ds[3];
- dw[8] = ds->ds[4];
-
- if (ilo_state_ds_get_scratch_size(ds)) {
- ilo_builder_batch_reloc64(builder, pos + 4, scratch_bo,
- ds->ds[1], 0);
- }
-}
-
-static inline void
-gen6_3DSTATE_GS(struct ilo_builder *builder,
- const struct ilo_state_gs *gs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 7;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- /* see gs_set_gen6_3DSTATE_GS() */
- dw[2] = gs->gs[0];
- dw[3] = gs->gs[1];
- dw[4] = gs->gs[2];
- dw[5] = gs->gs[3];
- dw[6] = gs->gs[4];
-
- if (ilo_state_gs_get_scratch_size(gs)) {
- ilo_builder_batch_reloc(builder, pos + 3, scratch_bo,
- gs->gs[1], 0);
- }
-}
-
-static inline void
-gen6_3DSTATE_GS_SVB_INDEX(struct ilo_builder *builder,
- int index, unsigned svbi,
- unsigned max_svbi,
- bool load_vertex_count)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
- assert(index >= 0 && index < 4);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_GS_SVB_INDEX) | (cmd_len - 2);
-
- dw[1] = index << GEN6_SVBI_DW1_INDEX__SHIFT;
- if (load_vertex_count)
- dw[1] |= GEN6_SVBI_DW1_LOAD_INTERNAL_VERTEX_COUNT;
-
- dw[2] = svbi;
- dw[3] = max_svbi;
-}
-
-static inline void
-gen7_3DSTATE_GS(struct ilo_builder *builder,
- const struct ilo_state_gs *gs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 7;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- /* see gs_set_gen7_3DSTATE_GS() */
- dw[2] = gs->gs[0];
- dw[3] = gs->gs[1];
- dw[4] = gs->gs[2];
- dw[5] = gs->gs[3];
- dw[6] = 0;
-
- if (ilo_state_gs_get_scratch_size(gs)) {
- ilo_builder_batch_reloc(builder, pos + 3, scratch_bo,
- gs->gs[1], 0);
- }
-}
-
-static inline void
-gen8_3DSTATE_GS(struct ilo_builder *builder,
- const struct ilo_state_gs *gs,
- uint32_t kernel_offset,
- struct intel_bo *scratch_bo)
-{
- const uint8_t cmd_len = 10;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
- dw[1] = kernel_offset;
- dw[2] = 0;
- /* see gs_set_gen7_3DSTATE_GS() */
- dw[3] = gs->gs[0];
- dw[4] = gs->gs[1];
- dw[5] = 0;
- dw[6] = gs->gs[2];
- dw[7] = gs->gs[3];
- dw[8] = 0;
- dw[9] = gs->gs[4];
-
- if (ilo_state_gs_get_scratch_size(gs)) {
- ilo_builder_batch_reloc64(builder, pos + 4, scratch_bo,
- gs->gs[1], 0);
- }
-}
-
-static inline void
-gen7_3DSTATE_STREAMOUT(struct ilo_builder *builder,
- const struct ilo_state_sol *sol)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 5 : 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_STREAMOUT) | (cmd_len - 2);
- /* see sol_set_gen7_3DSTATE_STREAMOUT() */
- dw[1] = sol->streamout[0];
- dw[2] = sol->streamout[1];
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[3] = sol->strides[1] << GEN8_SO_DW3_BUFFER1_PITCH__SHIFT |
- sol->strides[0] << GEN8_SO_DW3_BUFFER0_PITCH__SHIFT;
- dw[4] = sol->strides[3] << GEN8_SO_DW4_BUFFER3_PITCH__SHIFT |
- sol->strides[2] << GEN8_SO_DW4_BUFFER2_PITCH__SHIFT;
- }
-}
-
-static inline void
-gen7_3DSTATE_SO_DECL_LIST(struct ilo_builder *builder,
- const struct ilo_state_sol *sol)
-{
- /*
- * Note that "DWord Length" has 9 bits for this command and the type of
- * cmd_len cannot be uint8_t.
- */
- uint16_t cmd_len;
- int cmd_decl_count;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7.5)) {
- cmd_decl_count = sol->decl_count;
- } else {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 201:
- *
- * "Errata: All 128 decls for all four streams must be included
- * whenever this command is issued. The "Num Entries [n]" fields
- * still contain the actual numbers of valid decls."
- */
- cmd_decl_count = 128;
- }
-
- cmd_len = 3 + 2 * cmd_decl_count;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SO_DECL_LIST) | (cmd_len - 2);
- /* see sol_set_gen7_3DSTATE_SO_DECL_LIST() */
- dw[1] = sol->so_decl[0];
- dw[2] = sol->so_decl[1];
- memcpy(&dw[3], sol->decl, sizeof(sol->decl[0]) * sol->decl_count);
-
- if (sol->decl_count < cmd_decl_count) {
- memset(&dw[3 + 2 * sol->decl_count], 0, sizeof(sol->decl[0]) *
- cmd_decl_count - sol->decl_count);
- }
-}
-
-static inline void
-gen7_3DSTATE_SO_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_sol *sol,
- const struct ilo_state_sol_buffer *sb,
- uint8_t buffer)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- assert(buffer < ILO_STATE_SOL_MAX_BUFFER_COUNT);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SO_BUFFER) | (cmd_len - 2);
- /* see sol_buffer_set_gen7_3dstate_so_buffer() */
- dw[1] = buffer << GEN7_SO_BUF_DW1_INDEX__SHIFT |
- builder->mocs << GEN7_SO_BUF_DW1_MOCS__SHIFT |
- sol->strides[buffer] << GEN7_SO_BUF_DW1_PITCH__SHIFT;
-
- if (sb->vma) {
- ilo_builder_batch_reloc(builder, pos + 2, sb->vma->bo,
- sb->vma->bo_offset + sb->so_buf[0], INTEL_RELOC_WRITE);
- ilo_builder_batch_reloc(builder, pos + 3, sb->vma->bo,
- sb->vma->bo_offset + sb->so_buf[1], INTEL_RELOC_WRITE);
- } else {
- dw[2] = 0;
- dw[3] = 0;
- }
-}
-
-static inline void
-gen8_3DSTATE_SO_BUFFER(struct ilo_builder *builder,
- const struct ilo_state_sol *sol,
- const struct ilo_state_sol_buffer *sb,
- uint8_t buffer)
-{
- const uint8_t cmd_len = 8;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SO_BUFFER) | (cmd_len - 2);
- /* see sol_buffer_set_gen8_3dstate_so_buffer() */
- dw[1] = sb->so_buf[0] |
- buffer << GEN7_SO_BUF_DW1_INDEX__SHIFT |
- builder->mocs << GEN8_SO_BUF_DW1_MOCS__SHIFT;
-
- if (sb->vma) {
- ilo_builder_batch_reloc64(builder, pos + 2, sb->vma->bo,
- sb->vma->bo_offset + sb->so_buf[1], INTEL_RELOC_WRITE);
- } else {
- dw[2] = 0;
- dw[3] = 0;
- }
-
- dw[4] = sb->so_buf[2];
-
- if (sb->write_offset_vma) {
- ilo_builder_batch_reloc64(builder, pos + 5, sb->write_offset_vma->bo,
- sb->write_offset_vma->bo_offset + sizeof(uint32_t) * buffer,
- INTEL_RELOC_WRITE);
- } else {
- dw[5] = 0;
- dw[6] = 0;
- }
-
- dw[7] = sb->so_buf[3];
-}
-
-static inline void
-gen6_3DSTATE_BINDING_TABLE_POINTERS(struct ilo_builder *builder,
- uint32_t vs_binding_table,
- uint32_t gs_binding_table,
- uint32_t ps_binding_table)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_BINDING_TABLE_POINTERS) |
- GEN6_BINDING_TABLE_PTR_DW0_VS_CHANGED |
- GEN6_BINDING_TABLE_PTR_DW0_GS_CHANGED |
- GEN6_BINDING_TABLE_PTR_DW0_PS_CHANGED |
- (cmd_len - 2);
- dw[1] = vs_binding_table;
- dw[2] = gs_binding_table;
- dw[3] = ps_binding_table;
-}
-
-static inline void
-gen6_3DSTATE_SAMPLER_STATE_POINTERS(struct ilo_builder *builder,
- uint32_t vs_sampler_state,
- uint32_t gs_sampler_state,
- uint32_t ps_sampler_state)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLER_STATE_POINTERS) |
- GEN6_SAMPLER_PTR_DW0_VS_CHANGED |
- GEN6_SAMPLER_PTR_DW0_GS_CHANGED |
- GEN6_SAMPLER_PTR_DW0_PS_CHANGED |
- (cmd_len - 2);
- dw[1] = vs_sampler_state;
- dw[2] = gs_sampler_state;
- dw[3] = ps_sampler_state;
-}
-
-static inline void
-gen7_3dstate_pointer(struct ilo_builder *builder,
- int subop, uint32_t pointer)
-{
- const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
- GEN6_RENDER_SUBTYPE_3D |
- subop;
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2);
- dw[1] = pointer;
-}
-
-static inline void
-gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(struct ilo_builder *builder,
- uint32_t binding_table)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS,
- binding_table);
-}
-
-static inline void
-gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(struct ilo_builder *builder,
- uint32_t binding_table)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_HS,
- binding_table);
-}
-
-static inline void
-gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(struct ilo_builder *builder,
- uint32_t binding_table)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_DS,
- binding_table);
-}
-
-static inline void
-gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(struct ilo_builder *builder,
- uint32_t binding_table)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_GS,
- binding_table);
-}
-
-static inline void
-gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(struct ilo_builder *builder,
- uint32_t sampler_state)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_VS,
- sampler_state);
-}
-
-static inline void
-gen7_3DSTATE_SAMPLER_STATE_POINTERS_HS(struct ilo_builder *builder,
- uint32_t sampler_state)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_HS,
- sampler_state);
-}
-
-static inline void
-gen7_3DSTATE_SAMPLER_STATE_POINTERS_DS(struct ilo_builder *builder,
- uint32_t sampler_state)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_DS,
- sampler_state);
-}
-
-static inline void
-gen7_3DSTATE_SAMPLER_STATE_POINTERS_GS(struct ilo_builder *builder,
- uint32_t sampler_state)
-{
- gen7_3dstate_pointer(builder,
- GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_GS,
- sampler_state);
-}
-
-static inline void
-gen6_3dstate_constant(struct ilo_builder *builder, int subop,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
- GEN6_RENDER_SUBTYPE_3D |
- subop;
- const uint8_t cmd_len = 5;
- unsigned buf_enabled = 0x0;
- uint32_t buf_dw[4], *dw;
- int max_read_length, total_read_length;
- int i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 6);
-
- assert(num_bufs <= 4);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 138:
- *
- * "(3DSTATE_CONSTANT_VS) The sum of all four read length fields (each
- * incremented to represent the actual read length) must be less than
- * or equal to 32"
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 161:
- *
- * "(3DSTATE_CONSTANT_GS) The sum of all four read length fields (each
- * incremented to represent the actual read length) must be less than
- * or equal to 64"
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 287:
- *
- * "(3DSTATE_CONSTANT_PS) The sum of all four read length fields (each
- * incremented to represent the actual read length) must be less than
- * or equal to 64"
- */
- switch (subop) {
- case GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS:
- max_read_length = 32;
- break;
- case GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS:
- case GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS:
- max_read_length = 64;
- break;
- default:
- assert(!"unknown pcb subop");
- max_read_length = 0;
- break;
- }
-
- total_read_length = 0;
- for (i = 0; i < 4; i++) {
- if (i < num_bufs && sizes[i]) {
- /* in 256-bit units */
- const int read_len = (sizes[i] + 31) / 32;
-
- assert(bufs[i] % 32 == 0);
- assert(read_len <= 32);
-
- buf_enabled |= 1 << i;
- buf_dw[i] = bufs[i] | (read_len - 1);
-
- total_read_length += read_len;
- } else {
- buf_dw[i] = 0;
- }
- }
-
- assert(total_read_length <= max_read_length);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2) |
- buf_enabled << GEN6_CONSTANT_DW0_BUFFER_ENABLES__SHIFT |
- builder->mocs << GEN6_CONSTANT_DW0_MOCS__SHIFT;
-
- memcpy(&dw[1], buf_dw, sizeof(buf_dw));
-}
-
-static inline void
-gen6_3DSTATE_CONSTANT_VS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen6_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen6_3DSTATE_CONSTANT_GS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen6_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3dstate_constant(struct ilo_builder *builder,
- int subop,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
- GEN6_RENDER_SUBTYPE_3D |
- subop;
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 11 : 7;
- uint32_t payload[6], *dw;
- int total_read_length, i;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- /* VS, HS, DS, GS, and PS variants */
- assert(subop >= GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS &&
- subop <= GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS &&
- subop != GEN6_RENDER_OPCODE_3DSTATE_SAMPLE_MASK);
-
- assert(num_bufs <= 4);
-
- payload[0] = 0;
- payload[1] = 0;
-
- total_read_length = 0;
- for (i = 0; i < 4; i++) {
- int read_len;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 112:
- *
- * "Constant buffers must be enabled in order from Constant Buffer 0
- * to Constant Buffer 3 within this command. For example, it is
- * not allowed to enable Constant Buffer 1 by programming a
- * non-zero value in the VS Constant Buffer 1 Read Length without a
- * non-zero value in VS Constant Buffer 0 Read Length."
- */
- if (i >= num_bufs || !sizes[i]) {
- for (; i < 4; i++) {
- assert(i >= num_bufs || !sizes[i]);
- payload[2 + i] = 0;
- }
- break;
- }
-
- /* read lengths are in 256-bit units */
- read_len = (sizes[i] + 31) / 32;
- /* the lower 5 bits are used for memory object control state */
- assert(bufs[i] % 32 == 0);
-
- payload[i / 2] |= read_len << ((i % 2) ? 16 : 0);
- payload[2 + i] = bufs[i];
-
- total_read_length += read_len;
- }
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 113:
- *
- * "The sum of all four read length fields must be less than or equal
- * to the size of 64"
- */
- assert(total_read_length <= 64);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = cmd | (cmd_len - 2);
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[1] = payload[0];
- dw[2] = payload[1];
- dw[3] = payload[2];
- dw[4] = 0;
- dw[5] = payload[3];
- dw[6] = 0;
- dw[7] = payload[4];
- dw[8] = 0;
- dw[9] = payload[5];
- dw[10] = 0;
- } else {
- payload[2] |= builder->mocs << GEN7_CONSTANT_DW_ADDR_MOCS__SHIFT;
-
- memcpy(&dw[1], payload, sizeof(payload));
- }
-}
-
-static inline void
-gen7_3DSTATE_CONSTANT_VS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen7_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3DSTATE_CONSTANT_HS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen7_3dstate_constant(builder, GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_HS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3DSTATE_CONSTANT_DS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen7_3dstate_constant(builder, GEN7_RENDER_OPCODE_3DSTATE_CONSTANT_DS,
- bufs, sizes, num_bufs);
-}
-
-static inline void
-gen7_3DSTATE_CONSTANT_GS(struct ilo_builder *builder,
- const uint32_t *bufs, const int *sizes,
- int num_bufs)
-{
- gen7_3dstate_constant(builder, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_GS,
- bufs, sizes, num_bufs);
-}
-
-static inline uint32_t
-gen6_BINDING_TABLE_STATE(struct ilo_builder *builder,
- const uint32_t *surface_states,
- int num_surface_states)
-{
- const int state_align = 32;
- const int state_len = num_surface_states;
- uint32_t state_offset, *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 69:
- *
- * "It is stored as an array of up to 256 elements..."
- */
- assert(num_surface_states <= 256);
-
- if (!num_surface_states)
- return 0;
-
- state_offset = ilo_builder_surface_pointer(builder,
- ILO_BUILDER_ITEM_BINDING_TABLE, state_align, state_len, &dw);
- memcpy(dw, surface_states, state_len << 2);
-
- return state_offset;
-}
-
-static inline uint32_t
-gen6_SURFACE_STATE(struct ilo_builder *builder,
- const struct ilo_state_surface *surf)
-{
- int state_align, state_len;
- uint32_t state_offset, *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- state_align = 64;
- state_len = 13;
-
- state_offset = ilo_builder_surface_pointer(builder,
- ILO_BUILDER_ITEM_SURFACE, state_align, state_len, &dw);
- memcpy(dw, surf->surface, state_len << 2);
-
- if (surf->vma) {
- const uint32_t mocs = (surf->scanout) ?
- (GEN8_MOCS_MT_PTE | GEN8_MOCS_CT_L3) : builder->mocs;
-
- dw[1] |= mocs << GEN8_SURFACE_DW1_MOCS__SHIFT;
-
- ilo_builder_surface_reloc64(builder, state_offset, 8, surf->vma->bo,
- surf->vma->bo_offset + surf->surface[8],
- (surf->readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- } else {
- state_align = 32;
- state_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 8 : 6;
-
- state_offset = ilo_builder_surface_pointer(builder,
- ILO_BUILDER_ITEM_SURFACE, state_align, state_len, &dw);
- memcpy(dw, surf->surface, state_len << 2);
-
- if (surf->vma) {
- /*
- * For scanouts, we should not enable caching in LLC. Since we only
- * enable that on Gen8+, we are fine here.
- */
- dw[5] |= builder->mocs << GEN6_SURFACE_DW5_MOCS__SHIFT;
-
- ilo_builder_surface_reloc(builder, state_offset, 1, surf->vma->bo,
- surf->vma->bo_offset + surf->surface[1],
- (surf->readonly) ? 0 : INTEL_RELOC_WRITE);
- }
- }
-
- return state_offset;
-}
-
-static inline uint32_t
-gen6_SAMPLER_STATE(struct ilo_builder *builder,
- const struct ilo_state_sampler *samplers,
- const uint32_t *sampler_border_colors,
- int sampler_count)
-{
- const int state_align = 32;
- const int state_len = 4 * sampler_count;
- uint32_t state_offset, *dw;
- int i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 101:
- *
- * "The sampler state is stored as an array of up to 16 elements..."
- */
- assert(sampler_count <= 16);
-
- if (!sampler_count)
- return 0;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 132:
- *
- * "(Sampler Count of 3DSTATE_VS) Specifies how many samplers (in
- * multiples of 4) the vertex shader 0 kernel uses. Used only for
- * prefetching the associated sampler state entries.
- *
- * It also applies to other shader stages.
- */
- ilo_builder_dynamic_pad_top(builder, 4 * (4 - (sampler_count % 4)));
-
- state_offset = ilo_builder_dynamic_pointer(builder,
- ILO_BUILDER_ITEM_SAMPLER, state_align, state_len, &dw);
-
- for (i = 0; i < sampler_count; i++) {
- /* see sampler_set_gen6_SAMPLER_STATE() */
- dw[0] = samplers[i].sampler[0];
- dw[1] = samplers[i].sampler[1];
- dw[3] = samplers[i].sampler[2];
-
- assert(!(sampler_border_colors[i] & 0x1f));
- dw[2] = sampler_border_colors[i];
-
- dw += 4;
- }
-
- return state_offset;
-}
-
-static inline uint32_t
-gen6_SAMPLER_BORDER_COLOR_STATE(struct ilo_builder *builder,
- const struct ilo_state_sampler_border *border)
-{
- const int state_align =
- (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 64 : 32;
- const int state_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ? 4 : 12;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- /*
- * see border_set_gen6_SAMPLER_BORDER_COLOR_STATE() and
- * border_set_gen7_SAMPLER_BORDER_COLOR_STATE()
- */
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_BLOB,
- state_align, state_len, border->color);
-}
-
-static inline uint32_t
-gen6_push_constant_buffer(struct ilo_builder *builder,
- int size, void **pcb)
-{
- /*
- * For all VS, GS, FS, and CS push constant buffers, they must be aligned
- * to 32 bytes, and their sizes are specified in 256-bit units.
- */
- const int state_align = 32;
- const int state_len = align(size, 32) / 4;
- uint32_t state_offset;
- char *buf;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- state_offset = ilo_builder_dynamic_pointer(builder,
- ILO_BUILDER_ITEM_BLOB, state_align, state_len, (uint32_t **) &buf);
-
- /* zero out the unused range */
- if (size < state_len * 4)
- memset(&buf[size], 0, state_len * 4 - size);
-
- if (pcb)
- *pcb = buf;
-
- return state_offset;
-}
-
-static inline uint32_t
-gen6_user_vertex_buffer(struct ilo_builder *builder,
- int size, const void *vertices)
-{
- const int state_align = 8;
- const int state_len = size / 4;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- assert(size % 4 == 0);
-
- return ilo_builder_dynamic_write(builder, ILO_BUILDER_ITEM_BLOB,
- state_align, state_len, vertices);
-}
-
-#endif /* ILO_BUILDER_3D_TOP_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_blt.h b/src/gallium/drivers/ilo/core/ilo_builder_blt.h
deleted file mode 100644
index 4cc55984334..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_builder_blt.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_BLT_H
-#define ILO_BUILDER_BLT_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_builder.h"
-
-enum gen6_blt_mask {
- GEN6_BLT_MASK_8,
- GEN6_BLT_MASK_16,
- GEN6_BLT_MASK_32,
- GEN6_BLT_MASK_32_LO,
- GEN6_BLT_MASK_32_HI,
-};
-
-struct gen6_blt_bo {
- struct intel_bo *bo;
- uint32_t offset;
- int16_t pitch;
-};
-
-struct gen6_blt_xy_bo {
- struct intel_bo *bo;
- uint32_t offset;
- int16_t pitch;
-
- enum gen_surface_tiling tiling;
- int16_t x, y;
-};
-
-/*
- * From the Sandy Bridge PRM, volume 1 part 5, page 7:
- *
- * "The BLT engine is capable of transferring very large quantities of
- * graphics data. Any graphics data read from and written to the
- * destination is permitted to represent a number of pixels that occupies
- * up to 65,536 scan lines and up to 32,768 bytes per scan line at the
- * destination. The maximum number of pixels that may be represented per
- * scan line's worth of graphics data depends on the color depth."
- */
-static const int gen6_blt_max_bytes_per_scanline = 32768;
-static const int gen6_blt_max_scanlines = 65536;
-
-static inline uint32_t
-gen6_blt_translate_value_mask(enum gen6_blt_mask value_mask)
-{
- switch (value_mask) {
- case GEN6_BLT_MASK_8: return GEN6_BLITTER_BR13_FORMAT_8;
- case GEN6_BLT_MASK_16: return GEN6_BLITTER_BR13_FORMAT_565;
- default: return GEN6_BLITTER_BR13_FORMAT_8888;
- }
-}
-
-static inline uint32_t
-gen6_blt_translate_value_cpp(enum gen6_blt_mask value_mask)
-{
- switch (value_mask) {
- case GEN6_BLT_MASK_8: return 1;
- case GEN6_BLT_MASK_16: return 2;
- default: return 4;
- }
-}
-
-static inline uint32_t
-gen6_blt_translate_write_mask(enum gen6_blt_mask write_mask)
-{
- switch (write_mask) {
- case GEN6_BLT_MASK_32: return GEN6_BLITTER_BR00_WRITE_RGB |
- GEN6_BLITTER_BR00_WRITE_A;
- case GEN6_BLT_MASK_32_LO: return GEN6_BLITTER_BR00_WRITE_RGB;
- case GEN6_BLT_MASK_32_HI: return GEN6_BLITTER_BR00_WRITE_A;
- default: return 0;
- }
-}
-
-static inline void
-gen6_COLOR_BLT(struct ilo_builder *builder,
- const struct gen6_blt_bo *dst, uint32_t pattern,
- uint16_t width, uint16_t height, uint8_t rop,
- enum gen6_blt_mask value_mask,
- enum gen6_blt_mask write_mask)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 6 : 5;
- const int cpp = gen6_blt_translate_value_cpp(value_mask);
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(width < gen6_blt_max_bytes_per_scanline);
- assert(height < gen6_blt_max_scanlines);
- /* offsets are naturally aligned and pitches are dword-aligned */
- assert(dst->offset % cpp == 0 && dst->pitch % 4 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_BLITTER_CMD(COLOR_BLT) |
- gen6_blt_translate_write_mask(write_mask) |
- (cmd_len - 2);
- dw[1] = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
- gen6_blt_translate_value_mask(value_mask) |
- dst->pitch;
- dw[2] = height << 16 | width;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[5] = pattern;
-
- ilo_builder_batch_reloc64(builder, pos + 3,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- } else {
- dw[4] = pattern;
-
- ilo_builder_batch_reloc(builder, pos + 3,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- }
-}
-
-static inline void
-gen6_XY_COLOR_BLT(struct ilo_builder *builder,
- const struct gen6_blt_xy_bo *dst, uint32_t pattern,
- uint16_t width, uint16_t height, uint8_t rop,
- enum gen6_blt_mask value_mask,
- enum gen6_blt_mask write_mask)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 7 : 6;
- const int cpp = gen6_blt_translate_value_cpp(value_mask);
- int dst_align = 4, dst_pitch_shift = 0;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(width * cpp < gen6_blt_max_bytes_per_scanline);
- assert(height < gen6_blt_max_scanlines);
- /* INT16_MAX */
- assert(dst->x + width <= 32767 && dst->y + height <= 32767);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_BLITTER_CMD(XY_COLOR_BLT) |
- gen6_blt_translate_write_mask(write_mask) |
- (cmd_len - 2);
-
- if (dst->tiling != GEN6_TILING_NONE) {
- dw[0] |= GEN6_BLITTER_BR00_DST_TILED;
-
- assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y);
- dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512;
- /* in dwords when tiled */
- dst_pitch_shift = 2;
- }
-
- assert(dst->offset % dst_align == 0 && dst->pitch % dst_align == 0);
-
- dw[1] = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
- gen6_blt_translate_value_mask(value_mask) |
- dst->pitch >> dst_pitch_shift;
- dw[2] = dst->y << 16 | dst->x;
- dw[3] = (dst->y + height) << 16 | (dst->x + width);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[6] = pattern;
-
- ilo_builder_batch_reloc64(builder, pos + 4,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- } else {
- dw[5] = pattern;
-
- ilo_builder_batch_reloc(builder, pos + 4,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- }
-}
-
-static inline void
-gen6_SRC_COPY_BLT(struct ilo_builder *builder,
- const struct gen6_blt_bo *dst,
- const struct gen6_blt_bo *src,
- uint16_t width, uint16_t height, uint8_t rop,
- enum gen6_blt_mask value_mask,
- enum gen6_blt_mask write_mask)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 8 : 6;
- const int cpp = gen6_blt_translate_value_cpp(value_mask);
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(width < gen6_blt_max_bytes_per_scanline);
- assert(height < gen6_blt_max_scanlines);
- /* offsets are naturally aligned and pitches are dword-aligned */
- assert(dst->offset % cpp == 0 && dst->pitch % 4 == 0);
- assert(src->offset % cpp == 0 && src->pitch % 4 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_BLITTER_CMD(SRC_COPY_BLT) |
- gen6_blt_translate_write_mask(write_mask) |
- (cmd_len - 2);
- dw[1] = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
- gen6_blt_translate_value_mask(value_mask) |
- dst->pitch;
- dw[2] = height << 16 | width;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[5] = src->pitch;
-
- ilo_builder_batch_reloc64(builder, pos + 3,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- ilo_builder_batch_reloc64(builder, pos + 6, src->bo, src->offset, 0);
- } else {
- dw[4] = src->pitch;
-
- ilo_builder_batch_reloc(builder, pos + 3,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- ilo_builder_batch_reloc(builder, pos + 5, src->bo, src->offset, 0);
- }
-}
-
-static inline void
-gen6_XY_SRC_COPY_BLT(struct ilo_builder *builder,
- const struct gen6_blt_xy_bo *dst,
- const struct gen6_blt_xy_bo *src,
- uint16_t width, uint16_t height, uint8_t rop,
- enum gen6_blt_mask value_mask,
- enum gen6_blt_mask write_mask)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 10 : 8;
- const int cpp = gen6_blt_translate_value_cpp(value_mask);
- int dst_align = 4, dst_pitch_shift = 0;
- int src_align = 4, src_pitch_shift = 0;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(width * cpp < gen6_blt_max_bytes_per_scanline);
- assert(height < gen6_blt_max_scanlines);
- /* INT16_MAX */
- assert(dst->x + width <= 32767 && dst->y + height <= 32767);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_BLITTER_CMD(XY_SRC_COPY_BLT) |
- gen6_blt_translate_write_mask(write_mask) |
- (cmd_len - 2);
-
- if (dst->tiling != GEN6_TILING_NONE) {
- dw[0] |= GEN6_BLITTER_BR00_DST_TILED;
-
- assert(dst->tiling == GEN6_TILING_X || dst->tiling == GEN6_TILING_Y);
- dst_align = (dst->tiling == GEN6_TILING_Y) ? 128 : 512;
- /* in dwords when tiled */
- dst_pitch_shift = 2;
- }
-
- if (src->tiling != GEN6_TILING_NONE) {
- dw[0] |= GEN6_BLITTER_BR00_SRC_TILED;
-
- assert(src->tiling == GEN6_TILING_X || src->tiling == GEN6_TILING_Y);
- src_align = (src->tiling == GEN6_TILING_Y) ? 128 : 512;
- /* in dwords when tiled */
- src_pitch_shift = 2;
- }
-
- assert(dst->offset % dst_align == 0 && dst->pitch % dst_align == 0);
- assert(src->offset % src_align == 0 && src->pitch % src_align == 0);
-
- dw[1] = rop << GEN6_BLITTER_BR13_ROP__SHIFT |
- gen6_blt_translate_value_mask(value_mask) |
- dst->pitch >> dst_pitch_shift;
- dw[2] = dst->y << 16 | dst->x;
- dw[3] = (dst->y + height) << 16 | (dst->x + width);
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[6] = src->y << 16 | src->x;
- dw[7] = src->pitch >> src_pitch_shift;
-
- ilo_builder_batch_reloc64(builder, pos + 4,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- ilo_builder_batch_reloc64(builder, pos + 8, src->bo, src->offset, 0);
- } else {
- dw[5] = src->y << 16 | src->x;
- dw[6] = src->pitch >> src_pitch_shift;
-
- ilo_builder_batch_reloc(builder, pos + 4,
- dst->bo, dst->offset, INTEL_RELOC_WRITE);
- ilo_builder_batch_reloc(builder, pos + 7, src->bo, src->offset, 0);
- }
-}
-
-#endif /* ILO_BUILDER_BLT_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_decode.c b/src/gallium/drivers/ilo/core/ilo_builder_decode.c
deleted file mode 100644
index c5a98c91204..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_builder_decode.c
+++ /dev/null
@@ -1,685 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include <stdio.h>
-#include <stdarg.h>
-#include "genhw/genhw.h"
-#include "../shader/toy_compiler.h"
-
-#include "intel_winsys.h"
-#include "ilo_builder.h"
-
-static const uint32_t *
-writer_pointer(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned offset)
-{
- const struct ilo_builder_writer *writer = &builder->writers[which];
- return (const uint32_t *) ((const char *) writer->ptr + offset);
-}
-
-static uint32_t _util_printf_format(5, 6)
-writer_dw(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- unsigned offset, unsigned dw_index,
- const char *format, ...)
-{
- const uint32_t *dw = writer_pointer(builder, which, offset);
- va_list ap;
- char desc[16];
- int len;
-
- ilo_printf("0x%08x: 0x%08x: ",
- offset + (dw_index << 2), dw[dw_index]);
-
- va_start(ap, format);
- len = vsnprintf(desc, sizeof(desc), format, ap);
- va_end(ap);
-
- if (len >= sizeof(desc)) {
- len = sizeof(desc) - 1;
- desc[len] = '\0';
- }
-
- if (desc[len - 1] == '\n') {
- desc[len - 1] = '\0';
- ilo_printf("%8s: \n", desc);
- } else {
- ilo_printf("%8s: ", desc);
- }
-
- return dw[dw_index];
-}
-
-static void
-writer_decode_blob(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t);
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i += 4) {
- const uint32_t *dw = writer_pointer(builder, which, offset);
-
- writer_dw(builder, which, offset, 0, "BLOB%d", i / 4);
-
- switch (count - i) {
- case 1:
- ilo_printf("(%10.4f, %10c, %10c, %10c) "
- "(0x%08x, %10c, %10c, %10c)\n",
- uif(dw[0]), 'X', 'X', 'X',
- dw[0], 'X', 'X', 'X');
- break;
- case 2:
- ilo_printf("(%10.4f, %10.4f, %10c, %10c) "
- "(0x%08x, 0x%08x, %10c, %10c)\n",
- uif(dw[0]), uif(dw[1]), 'X', 'X',
- dw[0], dw[1], 'X', 'X');
- break;
- case 3:
- ilo_printf("(%10.4f, %10.4f, %10.4f, %10c) "
- "(0x%08x, 0x%08x, 0x%08x, %10c)\n",
- uif(dw[0]), uif(dw[1]), uif(dw[2]), 'X',
- dw[0], dw[1], dw[2], 'X');
- break;
- default:
- ilo_printf("(%10.4f, %10.4f, %10.4f, %10.4f) "
- "(0x%08x, 0x%08x, 0x%08x, 0x%08x)\n",
- uif(dw[0]), uif(dw[1]), uif(dw[2]), uif(dw[3]),
- dw[0], dw[1], dw[2], dw[3]);
- break;
- }
-
- offset += state_size * 4;
- }
-}
-
-static void
-writer_decode_clip_viewport(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 4;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- uint32_t dw;
-
- dw = writer_dw(builder, which, offset, 0, "CLIP VP%d", i);
- ilo_printf("xmin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 1, "CLIP VP%d", i);
- ilo_printf("xmax = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 2, "CLIP VP%d", i);
- ilo_printf("ymin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 3, "CLIP VP%d", i);
- ilo_printf("ymax = %f\n", uif(dw));
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_sf_clip_viewport_gen7(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 16;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- uint32_t dw;
-
- dw = writer_dw(builder, which, offset, 0, "SF_CLIP VP%d", i);
- ilo_printf("m00 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 1, "SF_CLIP VP%d", i);
- ilo_printf("m11 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 2, "SF_CLIP VP%d", i);
- ilo_printf("m22 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 3, "SF_CLIP VP%d", i);
- ilo_printf("m30 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 4, "SF_CLIP VP%d", i);
- ilo_printf("m31 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 5, "SF_CLIP VP%d", i);
- ilo_printf("m32 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 8, "SF_CLIP VP%d", i);
- ilo_printf("guardband xmin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 9, "SF_CLIP VP%d", i);
- ilo_printf("guardband xmax = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 10, "SF_CLIP VP%d", i);
- ilo_printf("guardband ymin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 11, "SF_CLIP VP%d", i);
- ilo_printf("guardband ymax = %f\n", uif(dw));
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw = writer_dw(builder, which, offset, 12, "SF_CLIP VP%d", i);
- ilo_printf("extent xmin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 13, "SF_CLIP VP%d", i);
- ilo_printf("extent xmax = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 14, "SF_CLIP VP%d", i);
- ilo_printf("extent ymin = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 15, "SF_CLIP VP%d", i);
- ilo_printf("extent ymax = %f\n", uif(dw));
- }
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_sf_viewport_gen6(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 8;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- uint32_t dw;
-
- dw = writer_dw(builder, which, offset, 0, "SF VP%d", i);
- ilo_printf("m00 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 1, "SF VP%d", i);
- ilo_printf("m11 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 2, "SF VP%d", i);
- ilo_printf("m22 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 3, "SF VP%d", i);
- ilo_printf("m30 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 4, "SF VP%d", i);
- ilo_printf("m31 = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 5, "SF VP%d", i);
- ilo_printf("m32 = %f\n", uif(dw));
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_sf_viewport(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
- writer_decode_sf_clip_viewport_gen7(builder, which, item);
- else
- writer_decode_sf_viewport_gen6(builder, which, item);
-}
-
-static void
-writer_decode_scissor_rect(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 2;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- uint32_t dw;
-
- dw = writer_dw(builder, which, offset, 0, "SCISSOR%d", i);
- ilo_printf("xmin %d, ymin %d\n",
- GEN_EXTRACT(dw, GEN6_SCISSOR_DW0_MIN_X),
- GEN_EXTRACT(dw, GEN6_SCISSOR_DW0_MIN_Y));
-
- dw = writer_dw(builder, which, offset, 1, "SCISSOR%d", i);
- ilo_printf("xmax %d, ymax %d\n",
- GEN_EXTRACT(dw, GEN6_SCISSOR_DW1_MAX_X),
- GEN_EXTRACT(dw, GEN6_SCISSOR_DW1_MAX_Y));
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_cc_viewport(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 2;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- uint32_t dw;
-
- dw = writer_dw(builder, which, offset, 0, "CC VP%d", i);
- ilo_printf("min_depth = %f\n", uif(dw));
-
- dw = writer_dw(builder, which, offset, 1, "CC VP%d", i);
- ilo_printf("max_depth = %f\n", uif(dw));
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_color_calc(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- uint32_t dw;
-
- dw = writer_dw(builder, which, item->offset, 0, "CC");
- ilo_printf("alpha test format %s, round disable %d, "
- "stencil ref %d, bf stencil ref %d\n",
- GEN_EXTRACT(dw, GEN6_CC_DW0_ALPHATEST) ? "FLOAT32" : "UNORM8",
- (bool) (dw & GEN6_CC_DW0_ROUND_DISABLE_DISABLE),
- GEN_EXTRACT(dw, GEN6_CC_DW0_STENCIL_REF),
- GEN_EXTRACT(dw, GEN6_CC_DW0_STENCIL1_REF));
-
- writer_dw(builder, which, item->offset, 1, "CC\n");
-
- dw = writer_dw(builder, which, item->offset, 2, "CC");
- ilo_printf("constant red %f\n", uif(dw));
-
- dw = writer_dw(builder, which, item->offset, 3, "CC");
- ilo_printf("constant green %f\n", uif(dw));
-
- dw = writer_dw(builder, which, item->offset, 4, "CC");
- ilo_printf("constant blue %f\n", uif(dw));
-
- dw = writer_dw(builder, which, item->offset, 5, "CC");
- ilo_printf("constant alpha %f\n", uif(dw));
-}
-
-static void
-writer_decode_depth_stencil(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- uint32_t dw;
-
- dw = writer_dw(builder, which, item->offset, 0, "D_S");
- ilo_printf("stencil %sable, func %d, write %sable\n",
- (dw & GEN6_ZS_DW0_STENCIL_TEST_ENABLE) ? "en" : "dis",
- GEN_EXTRACT(dw, GEN6_ZS_DW0_STENCIL_FUNC),
- (dw & GEN6_ZS_DW0_STENCIL_WRITE_ENABLE) ? "en" : "dis");
-
- dw = writer_dw(builder, which, item->offset, 1, "D_S");
- ilo_printf("stencil test mask 0x%x, write mask 0x%x\n",
- GEN_EXTRACT(dw, GEN6_ZS_DW1_STENCIL_TEST_MASK),
- GEN_EXTRACT(dw, GEN6_ZS_DW1_STENCIL_WRITE_MASK));
-
- dw = writer_dw(builder, which, item->offset, 2, "D_S");
- ilo_printf("depth test %sable, func %d, write %sable\n",
- (dw & GEN6_ZS_DW2_DEPTH_TEST_ENABLE) ? "en" : "dis",
- GEN_EXTRACT(dw, GEN6_ZS_DW2_DEPTH_FUNC),
- (dw & GEN6_ZS_DW2_DEPTH_WRITE_ENABLE) ? "en" : "dis");
-}
-
-static void
-writer_decode_blend(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 2;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- writer_dw(builder, which, offset, 0, "BLEND\n");
- offset += 4;
- }
-
- for (i = 0; i < count; i++) {
- writer_dw(builder, which, offset, 0, "BLEND%d\n", i);
- writer_dw(builder, which, offset, 1, "BLEND%d\n", i);
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_sampler(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 4;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- writer_dw(builder, which, offset, 0, "WM SAMP%d", i);
- ilo_printf("filtering\n");
-
- writer_dw(builder, which, offset, 1, "WM SAMP%d", i);
- ilo_printf("wrapping, lod\n");
-
- writer_dw(builder, which, offset, 2, "WM SAMP%d", i);
- ilo_printf("default color pointer\n");
-
- writer_dw(builder, which, offset, 3, "WM SAMP%d", i);
- ilo_printf("chroma key, aniso\n");
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_interface_descriptor(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 8;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- writer_dw(builder, which, offset, 0, "IDRT[%d]", i);
- ilo_printf("kernel\n");
-
- writer_dw(builder, which, offset, 1, "IDRT[%d]", i);
- ilo_printf("spf, fp mode\n");
-
- writer_dw(builder, which, offset, 2, "IDRT[%d]", i);
- ilo_printf("sampler\n");
-
- writer_dw(builder, which, offset, 3, "IDRT[%d]", i);
- ilo_printf("binding table\n");
-
- writer_dw(builder, which, offset, 4, "IDRT[%d]", i);
- ilo_printf("curbe read len\n");
-
- writer_dw(builder, which, offset, 5, "IDRT[%d]", i);
- ilo_printf("rounding mode, slm size\n");
-
- writer_dw(builder, which, offset, 6, "IDRT[%d]", i);
- ilo_printf("cross-thread curbe read len\n");
-
- writer_dw(builder, which, offset, 7, "IDRT[%d]", i);
- ilo_printf("mbz\n");
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_surface_gen7(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- uint32_t dw;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw = writer_dw(builder, which, item->offset, 0, "SURF");
- ilo_printf("type 0x%x, format 0x%x, tiling %d, %s array\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW0_TYPE),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW0_FORMAT),
- GEN_EXTRACT(dw, GEN8_SURFACE_DW0_TILING),
- (dw & GEN7_SURFACE_DW0_IS_ARRAY) ? "is" : "not");
-
- writer_dw(builder, which, item->offset, 1, "SURF");
- ilo_printf("qpitch\n");
- } else {
- dw = writer_dw(builder, which, item->offset, 0, "SURF");
- ilo_printf("type 0x%x, format 0x%x, tiling %d, %s array\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW0_TYPE),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW0_FORMAT),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW0_TILING),
- (dw & GEN7_SURFACE_DW0_IS_ARRAY) ? "is" : "not");
-
- writer_dw(builder, which, item->offset, 1, "SURF");
- ilo_printf("offset\n");
- }
-
- dw = writer_dw(builder, which, item->offset, 2, "SURF");
- ilo_printf("%dx%d size\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW2_WIDTH),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW2_HEIGHT));
-
- dw = writer_dw(builder, which, item->offset, 3, "SURF");
- ilo_printf("depth %d, pitch %d\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW3_DEPTH),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW3_PITCH));
-
- dw = writer_dw(builder, which, item->offset, 4, "SURF");
- ilo_printf("min array element %d, array extent %d\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW4_RT_VIEW_EXTENT));
-
- dw = writer_dw(builder, which, item->offset, 5, "SURF");
- ilo_printf("mip base %d, mips %d, x,y offset: %d,%d\n",
- GEN_EXTRACT(dw, GEN7_SURFACE_DW5_MIN_LOD),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW5_MIP_COUNT_LOD),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW5_X_OFFSET),
- GEN_EXTRACT(dw, GEN7_SURFACE_DW5_Y_OFFSET));
-
- writer_dw(builder, which, item->offset, 6, "SURF\n");
- writer_dw(builder, which, item->offset, 7, "SURF\n");
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- writer_dw(builder, which, item->offset, 8, "SURF\n");
- writer_dw(builder, which, item->offset, 9, "SURF\n");
- writer_dw(builder, which, item->offset, 10, "SURF\n");
- writer_dw(builder, which, item->offset, 11, "SURF\n");
- writer_dw(builder, which, item->offset, 12, "SURF\n");
- }
-}
-
-static void
-writer_decode_surface_gen6(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- uint32_t dw;
-
- dw = writer_dw(builder, which, item->offset, 0, "SURF");
- ilo_printf("type 0x%x, format 0x%x\n",
- GEN_EXTRACT(dw, GEN6_SURFACE_DW0_TYPE),
- GEN_EXTRACT(dw, GEN6_SURFACE_DW0_FORMAT));
-
- writer_dw(builder, which, item->offset, 1, "SURF");
- ilo_printf("offset\n");
-
- dw = writer_dw(builder, which, item->offset, 2, "SURF");
- ilo_printf("%dx%d size, %d mips\n",
- GEN_EXTRACT(dw, GEN6_SURFACE_DW2_WIDTH),
- GEN_EXTRACT(dw, GEN6_SURFACE_DW2_HEIGHT),
- GEN_EXTRACT(dw, GEN6_SURFACE_DW2_MIP_COUNT_LOD));
-
- dw = writer_dw(builder, which, item->offset, 3, "SURF");
- ilo_printf("pitch %d, tiling %d\n",
- GEN_EXTRACT(dw, GEN6_SURFACE_DW3_PITCH),
- GEN_EXTRACT(dw, GEN6_SURFACE_DW3_TILING));
-
- dw = writer_dw(builder, which, item->offset, 4, "SURF");
- ilo_printf("mip base %d\n",
- GEN_EXTRACT(dw, GEN6_SURFACE_DW4_MIN_LOD));
-
- dw = writer_dw(builder, which, item->offset, 5, "SURF");
- ilo_printf("x,y offset: %d,%d\n",
- GEN_EXTRACT(dw, GEN6_SURFACE_DW5_X_OFFSET),
- GEN_EXTRACT(dw, GEN6_SURFACE_DW5_Y_OFFSET));
-}
-
-static void
-writer_decode_surface(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
- writer_decode_surface_gen7(builder, which, item);
- else
- writer_decode_surface_gen6(builder, which, item);
-}
-
-static void
-writer_decode_binding_table(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const unsigned state_size = sizeof(uint32_t) * 1;
- const unsigned count = item->size / state_size;
- unsigned offset = item->offset;
- unsigned i;
-
- for (i = 0; i < count; i++) {
- writer_dw(builder, which, offset, 0, "BIND");
- ilo_printf("BINDING_TABLE_STATE[%d]\n", i);
-
- offset += state_size;
- }
-}
-
-static void
-writer_decode_kernel(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item)
-{
- const void *kernel;
-
- ilo_printf("0x%08x:\n", item->offset);
- kernel = (const void *) writer_pointer(builder, which, item->offset);
- toy_compiler_disassemble(builder->dev, kernel, item->size, true);
-}
-
-static const struct {
- void (*func)(const struct ilo_builder *builder,
- enum ilo_builder_writer_type which,
- const struct ilo_builder_item *item);
-} writer_decode_table[ILO_BUILDER_ITEM_COUNT] = {
- [ILO_BUILDER_ITEM_BLOB] = { writer_decode_blob },
- [ILO_BUILDER_ITEM_CLIP_VIEWPORT] = { writer_decode_clip_viewport },
- [ILO_BUILDER_ITEM_SF_VIEWPORT] = { writer_decode_sf_viewport },
- [ILO_BUILDER_ITEM_SCISSOR_RECT] = { writer_decode_scissor_rect },
- [ILO_BUILDER_ITEM_CC_VIEWPORT] = { writer_decode_cc_viewport },
- [ILO_BUILDER_ITEM_COLOR_CALC] = { writer_decode_color_calc },
- [ILO_BUILDER_ITEM_DEPTH_STENCIL] = { writer_decode_depth_stencil },
- [ILO_BUILDER_ITEM_BLEND] = { writer_decode_blend },
- [ILO_BUILDER_ITEM_SAMPLER] = { writer_decode_sampler },
- [ILO_BUILDER_ITEM_INTERFACE_DESCRIPTOR] = { writer_decode_interface_descriptor },
- [ILO_BUILDER_ITEM_SURFACE] = { writer_decode_surface },
- [ILO_BUILDER_ITEM_BINDING_TABLE] = { writer_decode_binding_table },
- [ILO_BUILDER_ITEM_KERNEL] = { writer_decode_kernel },
-};
-
-static void
-ilo_builder_writer_decode_items(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
- int i;
-
- if (!writer->item_used)
- return;
-
- writer->ptr = intel_bo_map(writer->bo, false);
- if (!writer->ptr)
- return;
-
- for (i = 0; i < writer->item_used; i++) {
- const struct ilo_builder_item *item = &writer->items[i];
-
- writer_decode_table[item->type].func(builder, which, item);
- }
-
- intel_bo_unmap(writer->bo);
- writer->ptr = NULL;
-}
-
-static void
-ilo_builder_writer_decode(struct ilo_builder *builder,
- enum ilo_builder_writer_type which)
-{
- struct ilo_builder_writer *writer = &builder->writers[which];
-
- assert(writer->bo && !writer->ptr);
-
- switch (which) {
- case ILO_BUILDER_WRITER_BATCH:
- ilo_printf("decoding batch buffer: %d bytes\n", writer->used);
- if (writer->used)
- intel_winsys_decode_bo(builder->winsys, writer->bo, writer->used);
-
- ilo_printf("decoding dynamic/surface buffer: %d states\n",
- writer->item_used);
- ilo_builder_writer_decode_items(builder, which);
- break;
- case ILO_BUILDER_WRITER_INSTRUCTION:
- if (true) {
- ilo_printf("skipping instruction buffer: %d kernels\n",
- writer->item_used);
- } else {
- ilo_printf("decoding instruction buffer: %d kernels\n",
- writer->item_used);
-
- ilo_builder_writer_decode_items(builder, which);
- }
- break;
- default:
- break;
- }
-}
-
-/**
- * Decode the builder according to the recorded items. This can be called
- * only after a successful ilo_builder_end().
- */
-void
-ilo_builder_decode(struct ilo_builder *builder)
-{
- int i;
-
- assert(!builder->unrecoverable_error);
-
- for (i = 0; i < ILO_BUILDER_WRITER_COUNT; i++)
- ilo_builder_writer_decode(builder, i);
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_media.h b/src/gallium/drivers/ilo/core/ilo_builder_media.h
deleted file mode 100644
index 7197104a23e..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_builder_media.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_MEDIA_H
-#define ILO_BUILDER_MEDIA_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_state_compute.h"
-#include "ilo_builder.h"
-
-static inline void
-gen6_MEDIA_VFE_STATE(struct ilo_builder *builder,
- const struct ilo_state_compute *compute)
-{
- const uint8_t cmd_len = 8;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_VFE_STATE) | (cmd_len - 2);
- /* see compute_set_gen6_MEDIA_VFE_STATE() */
- dw[1] = compute->vfe[0];
- dw[2] = compute->vfe[1];
- dw[3] = 0;
- dw[4] = compute->vfe[2];
- dw[5] = 0;
- dw[6] = 0;
- dw[7] = 0;
-}
-
-static inline void
-gen6_MEDIA_CURBE_LOAD(struct ilo_builder *builder,
- uint32_t offset, unsigned size)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- assert(offset % 32 == 0 && size % 32 == 0);
- /* GPU hangs if size is zero */
- assert(size);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_CURBE_LOAD) | (cmd_len - 2);
- dw[1] = 0;
- dw[2] = size;
- dw[3] = offset;
-}
-
-static inline void
-gen6_MEDIA_INTERFACE_DESCRIPTOR_LOAD(struct ilo_builder *builder,
- uint32_t offset, unsigned size)
-{
- const uint8_t cmd_len = 4;
- const unsigned idrt_alloc =
- ((ilo_dev_gen(builder->dev) >= ILO_GEN(7.5)) ? 64 : 32) * 32;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- assert(offset % 32 == 0 && size % 32 == 0);
- assert(size && size <= idrt_alloc);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_INTERFACE_DESCRIPTOR_LOAD) |
- (cmd_len - 2);
- dw[1] = 0;
- dw[2] = size;
- dw[3] = offset;
-}
-
-static inline void
-gen6_MEDIA_STATE_FLUSH(struct ilo_builder *builder)
-{
- const uint8_t cmd_len = 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(MEDIA, MEDIA_STATE_FLUSH) | (cmd_len - 2);
- dw[1] = 0;
-}
-
-static inline void
-gen7_GPGPU_WALKER(struct ilo_builder *builder,
- const unsigned thread_group_offset[3],
- const unsigned thread_group_dim[3],
- unsigned thread_group_size,
- unsigned simd_size)
-{
- const uint8_t cmd_len = 11;
- uint32_t right_execmask, bottom_execmask;
- unsigned thread_count;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 7, 7.5);
-
- assert(simd_size == 16 || simd_size == 8);
-
- thread_count = (thread_group_size + simd_size - 1) / simd_size;
- assert(thread_count <= 64);
-
- right_execmask = thread_group_size % simd_size;
- if (right_execmask)
- right_execmask = (1 << right_execmask) - 1;
- else
- right_execmask = (1 << simd_size) - 1;
-
- bottom_execmask = 0xffffffff;
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_RENDER_CMD(MEDIA, GPGPU_WALKER) | (cmd_len - 2);
- dw[1] = 0; /* always first IDRT */
-
- dw[2] = (thread_count - 1) << GEN7_GPGPU_DW2_THREAD_MAX_X__SHIFT;
- if (simd_size == 16)
- dw[2] |= GEN7_GPGPU_DW2_SIMD_SIZE_SIMD16;
- else
- dw[2] |= GEN7_GPGPU_DW2_SIMD_SIZE_SIMD8;
-
- dw[3] = thread_group_offset[0];
- dw[4] = thread_group_dim[0];
- dw[5] = thread_group_offset[1];
- dw[6] = thread_group_dim[1];
- dw[7] = thread_group_offset[2];
- dw[8] = thread_group_dim[2];
-
- dw[9] = right_execmask;
- dw[10] = bottom_execmask;
-}
-
-static inline uint32_t
-gen6_INTERFACE_DESCRIPTOR_DATA(struct ilo_builder *builder,
- const struct ilo_state_compute *compute,
- const uint32_t *kernel_offsets,
- const uint32_t *sampler_offsets,
- const uint32_t *binding_table_offsets)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 2, page 34:
- *
- * "(Interface Descriptor Total Length) This field must have the same
- * alignment as the Interface Descriptor Data Start Address.
- *
- * It must be DQWord (32-byte) aligned..."
- *
- * From the Sandy Bridge PRM, volume 2 part 2, page 35:
- *
- * "(Interface Descriptor Data Start Address) Specifies the 32-byte
- * aligned address of the Interface Descriptor data."
- */
- const int state_align = 32;
- const int state_len = (32 / 4) * compute->idrt_count;
- uint32_t state_offset, *dw;
- int i;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- state_offset = ilo_builder_dynamic_pointer(builder,
- ILO_BUILDER_ITEM_INTERFACE_DESCRIPTOR, state_align, state_len, &dw);
-
- for (i = 0; i < compute->idrt_count; i++) {
- /* see compute_set_gen6_INTERFACE_DESCRIPTOR_DATA() */
- dw[0] = compute->idrt[i][0] + kernel_offsets[i];
- dw[1] = 0;
- dw[2] = compute->idrt[i][1] |
- sampler_offsets[i];
- dw[3] = compute->idrt[i][2] |
- binding_table_offsets[i];
- dw[4] = compute->idrt[i][3];
- dw[5] = compute->idrt[i][4];
- dw[6] = compute->idrt[i][5];
- dw[7] = 0;
-
- dw += 8;
- }
-
- return state_offset;
-}
-
-#endif /* ILO_BUILDER_MEDIA_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_mi.h b/src/gallium/drivers/ilo/core/ilo_builder_mi.h
deleted file mode 100644
index 7d1d2c9a072..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_builder_mi.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_MI_H
-#define ILO_BUILDER_MI_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_builder.h"
-
-static inline void
-gen6_MI_STORE_DATA_IMM(struct ilo_builder *builder,
- struct intel_bo *bo, uint32_t bo_offset,
- uint64_t val)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 6 : 5;
- uint32_t reloc_flags = INTEL_RELOC_WRITE;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(bo_offset % 8 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_MI_CMD(MI_STORE_DATA_IMM) | (cmd_len - 2);
- /* must use GGTT on GEN6 as in PIPE_CONTROL */
- if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
- dw[0] |= GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT;
- reloc_flags |= INTEL_RELOC_GGTT;
- }
-
- dw[1] = 0; /* MBZ */
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[4] = (uint32_t) val;
- dw[5] = (uint32_t) (val >> 32);
-
- ilo_builder_batch_reloc64(builder, pos + 2, bo, bo_offset, reloc_flags);
- } else {
- dw[3] = (uint32_t) val;
- dw[4] = (uint32_t) (val >> 32);
-
- ilo_builder_batch_reloc(builder, pos + 2, bo, bo_offset, reloc_flags);
- }
-}
-
-static inline void
-gen6_MI_LOAD_REGISTER_IMM(struct ilo_builder *builder,
- uint32_t reg, uint32_t val)
-{
- const uint8_t cmd_len = 3;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(reg % 4 == 0);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_MI_CMD(MI_LOAD_REGISTER_IMM) | (cmd_len - 2);
- dw[1] = reg;
- dw[2] = val;
-}
-
-static inline void
-gen6_MI_STORE_REGISTER_MEM(struct ilo_builder *builder, uint32_t reg,
- struct intel_bo *bo, uint32_t bo_offset)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 4 : 3;
- uint32_t reloc_flags = INTEL_RELOC_WRITE;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- assert(reg % 4 == 0 && bo_offset % 4 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_MI_CMD(MI_STORE_REGISTER_MEM) | (cmd_len - 2);
- dw[1] = reg;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- ilo_builder_batch_reloc64(builder, pos + 2, bo, bo_offset, reloc_flags);
- } else {
- /* must use GGTT on Gen6 as in PIPE_CONTROL */
- if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
- dw[0] |= GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT;
- reloc_flags |= INTEL_RELOC_GGTT;
- }
-
- ilo_builder_batch_reloc(builder, pos + 2, bo, bo_offset, reloc_flags);
- }
-}
-
-static inline void
-gen6_MI_FLUSH_DW(struct ilo_builder *builder)
-{
- const uint8_t cmd_len = 4;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_MI_CMD(MI_FLUSH_DW) | (cmd_len - 2);
- dw[1] = 0;
- dw[2] = 0;
- dw[3] = 0;
-}
-
-static inline void
-gen6_MI_REPORT_PERF_COUNT(struct ilo_builder *builder,
- struct intel_bo *bo, uint32_t bo_offset,
- uint32_t report_id)
-{
- const uint8_t cmd_len = 3;
- uint32_t reloc_flags = INTEL_RELOC_WRITE;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- assert(bo_offset % 64 == 0);
-
- /* must use GGTT on GEN6 as in PIPE_CONTROL */
- if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
- bo_offset |= GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT;
- reloc_flags |= INTEL_RELOC_GGTT;
- }
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_MI_CMD(MI_REPORT_PERF_COUNT) | (cmd_len - 2);
- dw[2] = report_id;
-
- ilo_builder_batch_reloc(builder, pos + 1, bo, bo_offset, reloc_flags);
-}
-
-static inline void
-gen7_MI_LOAD_REGISTER_MEM(struct ilo_builder *builder, uint32_t reg,
- struct intel_bo *bo, uint32_t bo_offset)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 4 : 3;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 7, 8);
-
- assert(reg % 4 == 0 && bo_offset % 4 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN7_MI_CMD(MI_LOAD_REGISTER_MEM) | (cmd_len - 2);
- dw[1] = reg;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
- ilo_builder_batch_reloc64(builder, pos + 2, bo, bo_offset, 0);
- else
- ilo_builder_batch_reloc(builder, pos + 2, bo, bo_offset, 0);
-}
-
-/**
- * Add a MI_BATCH_BUFFER_END to the batch buffer. Pad with MI_NOOP if
- * necessary.
- */
-static inline void
-gen6_mi_batch_buffer_end(struct ilo_builder *builder)
-{
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 107:
- *
- * "The batch buffer must be QWord aligned and a multiple of QWords in
- * length."
- */
- const bool pad = !(builder->writers[ILO_BUILDER_WRITER_BATCH].used & 0x7);
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- if (pad) {
- ilo_builder_batch_pointer(builder, 2, &dw);
- dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
- dw[1] = GEN6_MI_CMD(MI_NOOP);
- } else {
- ilo_builder_batch_pointer(builder, 1, &dw);
- dw[0] = GEN6_MI_CMD(MI_BATCH_BUFFER_END);
- }
-}
-
-#endif /* ILO_BUILDER_MI_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_builder_render.h b/src/gallium/drivers/ilo/core/ilo_builder_render.h
deleted file mode 100644
index e2191496439..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_builder_render.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_BUILDER_RENDER_H
-#define ILO_BUILDER_RENDER_H
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-#include "ilo_builder.h"
-
-static inline void
-gen6_STATE_SIP(struct ilo_builder *builder, uint32_t sip)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 3 : 2;
- uint32_t *dw;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(COMMON, STATE_SIP) | (cmd_len - 2);
- dw[1] = sip;
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8))
- dw[2] = 0;
-}
-
-static inline void
-gen6_PIPELINE_SELECT(struct ilo_builder *builder, int pipeline)
-{
- const uint8_t cmd_len = 1;
- const uint32_t dw0 = GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT) |
- pipeline;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- switch (pipeline) {
- case GEN6_PIPELINE_SELECT_DW0_SELECT_3D:
- case GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA:
- break;
- case GEN7_PIPELINE_SELECT_DW0_SELECT_GPGPU:
- assert(ilo_dev_gen(builder->dev) >= ILO_GEN(7));
- break;
- default:
- assert(!"unknown pipeline");
- break;
- }
-
- ilo_builder_batch_write(builder, cmd_len, &dw0);
-}
-
-static inline void
-gen6_PIPE_CONTROL(struct ilo_builder *builder, uint32_t dw1,
- struct intel_bo *bo, uint32_t bo_offset,
- uint64_t imm)
-{
- const uint8_t cmd_len = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 6 : 5;
- uint32_t reloc_flags = INTEL_RELOC_WRITE;
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 8);
-
- if (dw1 & GEN6_PIPE_CONTROL_CS_STALL) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 73:
- *
- * "1 of the following must also be set (when CS stall is set):
- *
- * * Depth Cache Flush Enable ([0] of DW1)
- * * Stall at Pixel Scoreboard ([1] of DW1)
- * * Depth Stall ([13] of DW1)
- * * Post-Sync Operation ([13] of DW1)
- * * Render Target Cache Flush Enable ([12] of DW1)
- * * Notify Enable ([8] of DW1)"
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 61:
- *
- * "One of the following must also be set (when CS stall is set):
- *
- * * Render Target Cache Flush Enable ([12] of DW1)
- * * Depth Cache Flush Enable ([0] of DW1)
- * * Stall at Pixel Scoreboard ([1] of DW1)
- * * Depth Stall ([13] of DW1)
- * * Post-Sync Operation ([13] of DW1)"
- */
- uint32_t bit_test = GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL |
- GEN6_PIPE_CONTROL_DEPTH_STALL;
-
- /* post-sync op */
- bit_test |= GEN6_PIPE_CONTROL_WRITE_IMM |
- GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT |
- GEN6_PIPE_CONTROL_WRITE_TIMESTAMP;
-
- if (ilo_dev_gen(builder->dev) == ILO_GEN(6))
- bit_test |= GEN6_PIPE_CONTROL_NOTIFY_ENABLE;
-
- assert(dw1 & bit_test);
- }
-
- if (dw1 & GEN6_PIPE_CONTROL_DEPTH_STALL) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 73:
- *
- * "Following bits must be clear (when Depth Stall is set):
- *
- * * Render Target Cache Flush Enable ([12] of DW1)
- * * Depth Cache Flush Enable ([0] of DW1)"
- */
- assert(!(dw1 & (GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH)));
- }
-
- switch (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK) {
- case GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT:
- case GEN6_PIPE_CONTROL_WRITE_TIMESTAMP:
- assert(!imm);
- break;
- default:
- break;
- }
-
- assert(bo_offset % 8 == 0);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(3D, PIPE_CONTROL) | (cmd_len - 2);
- dw[1] = dw1;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[4] = (uint32_t) imm;
- dw[5] = (uint32_t) (imm >> 32);
-
- if (bo) {
- ilo_builder_batch_reloc64(builder, pos + 2,
- bo, bo_offset, reloc_flags);
- } else {
- dw[2] = 0;
- dw[3] = 0;
- }
-
- } else {
- dw[3] = (uint32_t) imm;
- dw[4] = (uint32_t) (imm >> 32);
-
- if (bo) {
- /*
- * From the Sandy Bridge PRM, volume 1 part 3, page 19:
- *
- * "[DevSNB] PPGTT memory writes by MI_* (such as
- * MI_STORE_DATA_IMM) and PIPE_CONTROL are not supported."
- */
- if (ilo_dev_gen(builder->dev) == ILO_GEN(6)) {
- bo_offset |= GEN6_PIPE_CONTROL_DW2_USE_GGTT;
- reloc_flags |= INTEL_RELOC_GGTT;
- }
-
- ilo_builder_batch_reloc(builder, pos + 2,
- bo, bo_offset, reloc_flags);
- } else {
- dw[2] = 0;
- }
- }
-}
-
-static inline void
-ilo_builder_batch_patch_sba(struct ilo_builder *builder)
-{
- const struct ilo_builder_writer *inst =
- &builder->writers[ILO_BUILDER_WRITER_INSTRUCTION];
-
- if (!builder->sba_instruction_pos)
- return;
-
- if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- ilo_builder_batch_reloc64(builder, builder->sba_instruction_pos,
- inst->bo,
- builder->mocs << GEN8_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
- } else {
- ilo_builder_batch_reloc(builder, builder->sba_instruction_pos, inst->bo,
- builder->mocs << GEN6_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
- }
-}
-
-/**
- * Add a STATE_BASE_ADDRESS to the batch buffer. The relocation entry for the
- * instruction buffer is not added until ilo_builder_end() or next
- * gen6_state_base_address().
- */
-static inline void
-gen6_state_base_address(struct ilo_builder *builder, bool init_all)
-{
- const uint8_t cmd_len = 10;
- const struct ilo_builder_writer *bat =
- &builder->writers[ILO_BUILDER_WRITER_BATCH];
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 6, 7.5);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(COMMON, STATE_BASE_ADDRESS) | (cmd_len - 2);
- dw[1] = builder->mocs << GEN6_SBA_MOCS__SHIFT |
- builder->mocs << GEN6_SBA_DW1_GENERAL_STATELESS_MOCS__SHIFT |
- init_all;
-
- ilo_builder_batch_reloc(builder, pos + 2, bat->bo,
- builder->mocs << GEN6_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
- ilo_builder_batch_reloc(builder, pos + 3, bat->bo,
- builder->mocs << GEN6_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
-
- dw[4] = builder->mocs << GEN6_SBA_MOCS__SHIFT | init_all;
-
- /*
- * Since the instruction writer has WRITER_FLAG_APPEND set, it is tempting
- * not to set Instruction Base Address. The problem is that we do not know
- * if the bo has been or will be moved by the kernel. We need a relocation
- * entry because of that.
- *
- * And since we also set WRITER_FLAG_GROW, we have to wait until
- * ilo_builder_end(), when the final bo is known, to add the relocation
- * entry.
- */
- ilo_builder_batch_patch_sba(builder);
- builder->sba_instruction_pos = pos + 5;
-
- /* skip range checks */
- dw[6] = init_all;
- dw[7] = 0xfffff000 + init_all;
- dw[8] = 0xfffff000 + init_all;
- dw[9] = init_all;
-}
-
-static inline void
-gen8_state_base_address(struct ilo_builder *builder, bool init_all)
-{
- const uint8_t cmd_len = 16;
- const struct ilo_builder_writer *bat =
- &builder->writers[ILO_BUILDER_WRITER_BATCH];
- uint32_t *dw;
- unsigned pos;
-
- ILO_DEV_ASSERT(builder->dev, 8, 8);
-
- pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
-
- dw[0] = GEN6_RENDER_CMD(COMMON, STATE_BASE_ADDRESS) | (cmd_len - 2);
- dw[1] = builder->mocs << GEN8_SBA_MOCS__SHIFT | init_all;
- dw[2] = 0;
- dw[3] = builder->mocs << GEN8_SBA_DW3_STATELESS_MOCS__SHIFT;
- ilo_builder_batch_reloc64(builder, pos + 4, bat->bo,
- builder->mocs << GEN8_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
- ilo_builder_batch_reloc64(builder, pos + 6, bat->bo,
- builder->mocs << GEN8_SBA_MOCS__SHIFT | GEN6_SBA_ADDR_MODIFIED,
- 0);
- dw[8] = builder->mocs << GEN8_SBA_MOCS__SHIFT | init_all;
- dw[9] = 0;
-
- ilo_builder_batch_patch_sba(builder);
- builder->sba_instruction_pos = pos + 10;
-
- /* skip range checks */
- dw[12] = 0xfffff000 + init_all;
- dw[13] = 0xfffff000 + init_all;
- dw[14] = 0xfffff000 + init_all;
- dw[15] = 0xfffff000 + init_all;
-}
-
-#endif /* ILO_BUILDER_RENDER_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_core.h b/src/gallium/drivers/ilo/core/ilo_core.h
deleted file mode 100644
index cbc568c4cd0..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_core.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_CORE_H
-#define ILO_CORE_H
-
-#include "pipe/p_compiler.h"
-
-#include "util/u_math.h"
-
-#endif /* ILO_CORE_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_debug.c b/src/gallium/drivers/ilo/core/ilo_debug.c
deleted file mode 100644
index 168818bf4e2..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_debug.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-
-static const struct debug_named_value ilo_debug_flags[] = {
- { "batch", ILO_DEBUG_BATCH, "Dump batch/dynamic/surface/instruction buffers" },
- { "vs", ILO_DEBUG_VS, "Dump vertex shaders" },
- { "gs", ILO_DEBUG_GS, "Dump geometry shaders" },
- { "fs", ILO_DEBUG_FS, "Dump fragment shaders" },
- { "cs", ILO_DEBUG_CS, "Dump compute shaders" },
- { "draw", ILO_DEBUG_DRAW, "Show draw information" },
- { "submit", ILO_DEBUG_SUBMIT, "Show batch buffer submissions" },
- { "hang", ILO_DEBUG_HANG, "Detect GPU hangs" },
- { "nohw", ILO_DEBUG_NOHW, "Do not send commands to HW" },
- { "nocache", ILO_DEBUG_NOCACHE, "Always invalidate HW caches" },
- { "nohiz", ILO_DEBUG_NOHIZ, "Disable HiZ" },
- DEBUG_NAMED_VALUE_END
-};
-
-int ilo_debug;
-
-void
-ilo_debug_init(const char *name)
-{
- ilo_debug = debug_get_flags_option(name, ilo_debug_flags, 0);
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_debug.h b/src/gallium/drivers/ilo/core/ilo_debug.h
deleted file mode 100644
index 532a2aa7ed6..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_debug.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_DEBUG_H
-#define ILO_DEBUG_H
-
-#include "util/u_debug.h"
-
-#include "ilo_core.h"
-
-/* enable debug flags affecting hot pathes only with debug builds */
-#ifdef DEBUG
-#define ILO_DEBUG_HOT 1
-#else
-#define ILO_DEBUG_HOT 0
-#endif
-
-enum ilo_debug {
- ILO_DEBUG_BATCH = 1 << 0,
- ILO_DEBUG_VS = 1 << 1,
- ILO_DEBUG_GS = 1 << 2,
- ILO_DEBUG_FS = 1 << 3,
- ILO_DEBUG_CS = 1 << 4,
- ILO_DEBUG_DRAW = ILO_DEBUG_HOT << 5,
- ILO_DEBUG_SUBMIT = 1 << 6,
- ILO_DEBUG_HANG = 1 << 7,
-
- /* flags that affect the behaviors of the driver */
- ILO_DEBUG_NOHW = 1 << 20,
- ILO_DEBUG_NOCACHE = 1 << 21,
- ILO_DEBUG_NOHIZ = 1 << 22,
-};
-
-extern int ilo_debug;
-
-void
-ilo_debug_init(const char *name);
-
-/**
- * Print a message, for dumping or debugging.
- */
-static inline void _util_printf_format(1, 2)
-ilo_printf(const char *format, ...)
-{
- va_list ap;
-
- va_start(ap, format);
- _debug_vprintf(format, ap);
- va_end(ap);
-}
-
-/**
- * Print a critical error.
- */
-static inline void _util_printf_format(1, 2)
-ilo_err(const char *format, ...)
-{
- va_list ap;
-
- va_start(ap, format);
- _debug_vprintf(format, ap);
- va_end(ap);
-}
-
-/**
- * Print a warning, silenced for release builds.
- */
-static inline void _util_printf_format(1, 2)
-ilo_warn(const char *format, ...)
-{
-#ifdef DEBUG
- va_list ap;
-
- va_start(ap, format);
- _debug_vprintf(format, ap);
- va_end(ap);
-#else
-#endif
-}
-
-static inline bool
-ilo_is_zeroed(const void *ptr, size_t size)
-{
-#ifdef DEBUG
- size_t i;
-
- for (i = 0; i < size; i++) {
- if (*((const char *) ptr) != 0)
- return false;
- }
-
- return true;
-#else
- return true;
-#endif
-}
-
-#endif /* ILO_DEBUG_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_dev.c b/src/gallium/drivers/ilo/core/ilo_dev.c
deleted file mode 100644
index 925322abba4..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_dev.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "intel_winsys.h"
-
-#include "ilo_debug.h"
-#include "ilo_dev.h"
-
-/**
- * Initialize the \p dev from \p winsys.
- */
-bool
-ilo_dev_init(struct ilo_dev *dev, struct intel_winsys *winsys)
-{
- const struct intel_winsys_info *info;
-
- assert(ilo_is_zeroed(dev, sizeof(*dev)));
-
- info = intel_winsys_get_info(winsys);
-
- dev->winsys = winsys;
- dev->devid = info->devid;
- dev->aperture_total = info->aperture_total;
- dev->aperture_mappable = info->aperture_mappable;
- dev->has_llc = info->has_llc;
- dev->has_address_swizzling = info->has_address_swizzling;
- dev->has_logical_context = info->has_logical_context;
- dev->has_ppgtt = info->has_ppgtt;
- dev->has_timestamp = info->has_timestamp;
- dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
-
- if (!dev->has_logical_context) {
- ilo_err("missing hardware logical context support\n");
- return false;
- }
-
- /*
- * PIPE_CONTROL and MI_* use PPGTT writes on GEN7+ and privileged GGTT
- * writes on GEN6.
- *
- * From the Sandy Bridge PRM, volume 1 part 3, page 101:
- *
- * "[DevSNB] When Per-Process GTT Enable is set, it is assumed that all
- * code is in a secure environment, independent of address space.
- * Under this condition, this bit only specifies the address space
- * (GGTT or PPGTT). All commands are executed "as-is""
- *
- * We need PPGTT to be enabled on GEN6 too.
- */
- if (!dev->has_ppgtt) {
- /* experiments show that it does not really matter... */
- ilo_warn("PPGTT disabled\n");
- }
-
- if (gen_is_bdw(info->devid) || gen_is_chv(info->devid)) {
- dev->gen_opaque = ILO_GEN(8);
- dev->gt = (gen_is_bdw(info->devid)) ? gen_get_bdw_gt(info->devid) : 1;
- /* XXX random values */
- if (dev->gt == 3) {
- dev->eu_count = 48;
- dev->thread_count = 336;
- dev->urb_size = 384 * 1024;
- } else if (dev->gt == 2) {
- dev->eu_count = 24;
- dev->thread_count = 168;
- dev->urb_size = 384 * 1024;
- } else {
- dev->eu_count = 12;
- dev->thread_count = 84;
- dev->urb_size = 192 * 1024;
- }
- } else if (gen_is_hsw(info->devid)) {
- /*
- * From the Haswell PRM, volume 4, page 8:
- *
- * "Description GT3 GT2 GT1.5 GT1
- * (...)
- * EUs (Total) 40 20 12 10
- * Threads (Total) 280 140 84 70
- * (...)
- * URB Size (max, within L3$) 512KB 256KB 256KB 128KB
- */
- dev->gen_opaque = ILO_GEN(7.5);
- dev->gt = gen_get_hsw_gt(info->devid);
- if (dev->gt == 3) {
- dev->eu_count = 40;
- dev->thread_count = 280;
- dev->urb_size = 512 * 1024;
- } else if (dev->gt == 2) {
- dev->eu_count = 20;
- dev->thread_count = 140;
- dev->urb_size = 256 * 1024;
- } else {
- dev->eu_count = 10;
- dev->thread_count = 70;
- dev->urb_size = 128 * 1024;
- }
- } else if (gen_is_ivb(info->devid) || gen_is_vlv(info->devid)) {
- /*
- * From the Ivy Bridge PRM, volume 1 part 1, page 18:
- *
- * "Device # of EUs #Threads/EU
- * Ivy Bridge (GT2) 16 8
- * Ivy Bridge (GT1) 6 6"
- *
- * From the Ivy Bridge PRM, volume 4 part 2, page 17:
- *
- * "URB Size URB Rows URB Rows when SLM Enabled
- * 128k 4096 2048
- * 256k 8096 4096"
- */
- dev->gen_opaque = ILO_GEN(7);
- dev->gt = (gen_is_ivb(info->devid)) ? gen_get_ivb_gt(info->devid) : 1;
- if (dev->gt == 2) {
- dev->eu_count = 16;
- dev->thread_count = 128;
- dev->urb_size = 256 * 1024;
- } else {
- dev->eu_count = 6;
- dev->thread_count = 36;
- dev->urb_size = 128 * 1024;
- }
- } else if (gen_is_snb(info->devid)) {
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 22:
- *
- * "Device # of EUs #Threads/EU
- * SNB GT2 12 5
- * SNB GT1 6 4"
- *
- * From the Sandy Bridge PRM, volume 4 part 2, page 18:
- *
- * "[DevSNB]: The GT1 product's URB provides 32KB of storage,
- * arranged as 1024 256-bit rows. The GT2 product's URB provides
- * 64KB of storage, arranged as 2048 256-bit rows. A row
- * corresponds in size to an EU GRF register. Read/write access to
- * the URB is generally supported on a row-granular basis."
- */
- dev->gen_opaque = ILO_GEN(6);
- dev->gt = gen_get_snb_gt(info->devid);
- if (dev->gt == 2) {
- dev->eu_count = 12;
- dev->thread_count = 60;
- dev->urb_size = 64 * 1024;
- } else {
- dev->eu_count = 6;
- dev->thread_count = 24;
- dev->urb_size = 32 * 1024;
- }
- } else {
- ilo_err("unknown GPU generation\n");
- return false;
- }
-
- return true;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_dev.h b/src/gallium/drivers/ilo/core/ilo_dev.h
deleted file mode 100644
index a9f9b176e16..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_dev.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_DEV_H
-#define ILO_DEV_H
-
-#include "ilo_core.h"
-
-#define ILO_GEN(gen) ((int) (gen * 100))
-
-#define ILO_DEV_ASSERT(dev, min_gen, max_gen) \
- ilo_dev_assert(dev, ILO_GEN(min_gen), ILO_GEN(max_gen))
-
-struct intel_winsys;
-
-struct ilo_dev {
- struct intel_winsys *winsys;
-
- /* these mirror intel_winsys_info */
- int devid;
- size_t aperture_total;
- size_t aperture_mappable;
- bool has_llc;
- bool has_address_swizzling;
- bool has_logical_context;
- bool has_ppgtt;
- bool has_timestamp;
- bool has_gen7_sol_reset;
-
- /* use ilo_dev_gen() to access */
- int gen_opaque;
-
- int gt;
- int eu_count;
- int thread_count;
- int urb_size;
-};
-
-bool
-ilo_dev_init(struct ilo_dev *dev, struct intel_winsys *winsys);
-
-static inline int
-ilo_dev_gen(const struct ilo_dev *dev)
-{
- return dev->gen_opaque;
-}
-
-static inline void
-ilo_dev_assert(const struct ilo_dev *dev, int min_opqaue, int max_opqaue)
-{
- assert(dev->gen_opaque >= min_opqaue && dev->gen_opaque <= max_opqaue);
-}
-
-#endif /* ILO_DEV_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_image.c b/src/gallium/drivers/ilo/core/ilo_image.c
deleted file mode 100644
index 6eefc8f46d2..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_image.c
+++ /dev/null
@@ -1,1451 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_image.h"
-
-enum {
- IMAGE_TILING_NONE = 1 << GEN6_TILING_NONE,
- IMAGE_TILING_X = 1 << GEN6_TILING_X,
- IMAGE_TILING_Y = 1 << GEN6_TILING_Y,
- IMAGE_TILING_W = 1 << GEN8_TILING_W,
-
- IMAGE_TILING_ALL = (IMAGE_TILING_NONE |
- IMAGE_TILING_X |
- IMAGE_TILING_Y |
- IMAGE_TILING_W)
-};
-
-struct ilo_image_layout {
- enum ilo_image_walk_type walk;
- bool interleaved_samples;
-
- uint8_t valid_tilings;
- enum gen_surface_tiling tiling;
-
- enum ilo_image_aux_type aux;
-
- int align_i;
- int align_j;
-
- struct ilo_image_lod *lods;
- int walk_layer_h0;
- int walk_layer_h1;
- int walk_layer_height;
- int monolithic_width;
- int monolithic_height;
-};
-
-static enum ilo_image_walk_type
-image_get_gen6_walk(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /* TODO we want LODs to be page-aligned */
- if (info->type == GEN6_SURFTYPE_3D)
- return ILO_IMAGE_WALK_3D;
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 115:
- *
- * "The separate stencil buffer does not support mip mapping, thus the
- * storage for LODs other than LOD 0 is not needed. The following
- * QPitch equation applies only to the separate stencil buffer:
- *
- * QPitch = h_0"
- *
- * Use ILO_IMAGE_WALK_LOD and manually offset to the (page-aligned) levels
- * when bound.
- */
- if (info->bind_zs && info->format == GEN6_FORMAT_R8_UINT)
- return ILO_IMAGE_WALK_LOD;
-
- /* compact spacing is not supported otherwise */
- return ILO_IMAGE_WALK_LAYER;
-}
-
-static enum ilo_image_walk_type
-image_get_gen7_walk(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (info->type == GEN6_SURFTYPE_3D)
- return ILO_IMAGE_WALK_3D;
-
- /*
- * From the Ivy Bridge PRM, volume 1 part 1, page 111:
- *
- * "note that the depth buffer and stencil buffer have an implied value
- * of ARYSPC_FULL"
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 66:
- *
- * "If Multisampled Surface Storage Format is MSFMT_MSS and Number of
- * Multisamples is not MULTISAMPLECOUNT_1, this field (Surface Array
- * Spacing) must be set to ARYSPC_LOD0."
- */
- if (info->sample_count > 1)
- assert(info->level_count == 1);
- return (info->bind_zs || info->level_count > 1) ?
- ILO_IMAGE_WALK_LAYER : ILO_IMAGE_WALK_LOD;
-}
-
-static bool
-image_get_gen6_interleaved_samples(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * Gen6 supports only interleaved samples. It is not explicitly stated,
- * but on Gen7+, render targets are expected to be UMS/CMS (samples
- * non-interleaved) and depth/stencil buffers are expected to be IMS
- * (samples interleaved).
- *
- * See "Multisampled Surface Storage Format" field of SURFACE_STATE.
- */
- return (ilo_dev_gen(dev) == ILO_GEN(6) || info->bind_zs);
-}
-
-static uint8_t
-image_get_gen6_valid_tilings(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- uint8_t valid_tilings = IMAGE_TILING_ALL;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->valid_tilings)
- valid_tilings &= info->valid_tilings;
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 32:
- *
- * "Display/Overlay Y-Major not supported.
- * X-Major required for Async Flips"
- */
- if (unlikely(info->bind_scanout))
- valid_tilings &= IMAGE_TILING_X;
-
- /*
- * From the Sandy Bridge PRM, volume 3 part 2, page 158:
- *
- * "The cursor surface address must be 4K byte aligned. The cursor must
- * be in linear memory, it cannot be tiled."
- */
- if (unlikely(info->bind_cursor))
- valid_tilings &= IMAGE_TILING_NONE;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 318:
- *
- * "[DevSNB+]: This field (Tiled Surface) must be set to TRUE. Linear
- * Depth Buffer is not supported."
- *
- * "The Depth Buffer, if tiled, must use Y-Major tiling."
- *
- * From the Sandy Bridge PRM, volume 1 part 2, page 22:
- *
- * "W-Major Tile Format is used for separate stencil."
- */
- if (info->bind_zs) {
- if (info->format == GEN6_FORMAT_R8_UINT)
- valid_tilings &= IMAGE_TILING_W;
- else
- valid_tilings &= IMAGE_TILING_Y;
- }
-
- if (info->bind_surface_sampler ||
- info->bind_surface_dp_render ||
- info->bind_surface_dp_typed) {
- /*
- * From the Haswell PRM, volume 2d, page 233:
- *
- * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
- * (Tiled Surface) must be TRUE."
- */
- if (info->sample_count > 1)
- valid_tilings &= ~IMAGE_TILING_NONE;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8))
- valid_tilings &= ~IMAGE_TILING_W;
- }
-
- if (info->bind_surface_dp_render) {
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 32:
- *
- * "NOTE: 128BPE Format Color buffer ( render target ) MUST be
- * either TileX or Linear."
- *
- * From the Haswell PRM, volume 5, page 32:
- *
- * "NOTE: 128 BPP format color buffer (render target) supports
- * Linear, TiledX and TiledY."
- */
- if (ilo_dev_gen(dev) < ILO_GEN(7.5) && info->block_size == 16)
- valid_tilings &= ~IMAGE_TILING_Y;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 63:
- *
- * "This field (Surface Vertical Aligment) must be set to VALIGN_4
- * for all tiled Y Render Target surfaces."
- *
- * "VALIGN_4 is not supported for surface format R32G32B32_FLOAT."
- *
- * R32G32B32_FLOAT is not renderable and we only need an assert() here.
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && ilo_dev_gen(dev) <= ILO_GEN(7.5))
- assert(info->format != GEN6_FORMAT_R32G32B32_FLOAT);
- }
-
- return valid_tilings;
-}
-
-static uint64_t
-image_get_gen6_estimated_size(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- /* padding not considered */
- const uint64_t slice_size = info->width * info->height *
- info->block_size / (info->block_width * info->block_height);
- const uint64_t slice_count =
- info->depth * info->array_size * info->sample_count;
- const uint64_t estimated_size = slice_size * slice_count;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->level_count == 1)
- return estimated_size;
- else
- return estimated_size * 4 / 3;
-}
-
-static enum gen_surface_tiling
-image_get_gen6_tiling(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- uint8_t valid_tilings)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (valid_tilings) {
- case IMAGE_TILING_NONE:
- return GEN6_TILING_NONE;
- case IMAGE_TILING_X:
- return GEN6_TILING_X;
- case IMAGE_TILING_Y:
- return GEN6_TILING_Y;
- case IMAGE_TILING_W:
- return GEN8_TILING_W;
- default:
- break;
- }
-
- /*
- * X-tiling has the property that vertically adjacent pixels are usually in
- * the same page. When the image size is less than a page, the image
- * height is 1, or when the image is not accessed in blocks, there is no
- * reason to tile.
- *
- * Y-tiling is similar, where vertically adjacent pixels are usually in the
- * same cacheline.
- */
- if (valid_tilings & IMAGE_TILING_NONE) {
- const uint64_t estimated_size =
- image_get_gen6_estimated_size(dev, info);
-
- if (info->height == 1 || !(info->bind_surface_sampler ||
- info->bind_surface_dp_render ||
- info->bind_surface_dp_typed))
- return GEN6_TILING_NONE;
-
- if (estimated_size <= 64 || (info->prefer_linear_threshold &&
- estimated_size > info->prefer_linear_threshold))
- return GEN6_TILING_NONE;
-
- if (estimated_size <= 2048)
- valid_tilings &= ~IMAGE_TILING_X;
- }
-
- return (valid_tilings & IMAGE_TILING_Y) ? GEN6_TILING_Y :
- (valid_tilings & IMAGE_TILING_X) ? GEN6_TILING_X :
- GEN6_TILING_NONE;
-}
-
-static bool
-image_get_gen6_hiz_enable(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* depth buffer? */
- if (!info->bind_zs ||
- info->format == GEN6_FORMAT_R8_UINT ||
- info->interleaved_stencil)
- return false;
-
- /* we want to be able to force 8x4 alignments */
- if (info->type == GEN6_SURFTYPE_1D)
- return false;
-
- if (info->aux_disable)
- return false;
-
- if (ilo_debug & ILO_DEBUG_NOHIZ)
- return false;
-
- return true;
-}
-
-static bool
-image_get_gen7_mcs_enable(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- enum gen_surface_tiling tiling)
-{
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!info->bind_surface_sampler && !info->bind_surface_dp_render)
- return false;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 77:
- *
- * "For Render Target and Sampling Engine Surfaces:If the surface is
- * multisampled (Number of Multisamples any value other than
- * MULTISAMPLECOUNT_1), this field (MCS Enable) must be enabled."
- *
- * "This field must be set to 0 for all SINT MSRTs when all RT channels
- * are not written"
- */
- if (info->sample_count > 1) {
- if (ilo_dev_gen(dev) < ILO_GEN(8))
- assert(!info->is_integer);
- return true;
- }
-
- if (info->aux_disable)
- return false;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 326:
- *
- * "When MCS is buffer is used for color clear of non-multisampler
- * render target, the following restrictions apply.
- * - Support is limited to tiled render targets.
- * - Support is for non-mip-mapped and non-array surface types only.
- * - Clear is supported only on the full RT; i.e., no partial clear or
- * overlapping clears.
- * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
- * 64bpp and 128bpp.
- * ..."
- *
- * How about SURFTYPE_3D?
- */
- if (!info->bind_surface_dp_render ||
- tiling == GEN6_TILING_NONE ||
- info->level_count > 1 ||
- info->array_size > 1)
- return false;
-
- switch (info->block_size) {
- case 4:
- case 8:
- case 16:
- return true;
- default:
- return false;
- }
-}
-
-static void
-image_get_gen6_alignments(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- int *align_i, int *align_j)
-{
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 113:
- *
- * "surface format align_i align_j
- * YUV 4:2:2 formats 4 *see below
- * BC1-5 4 4
- * FXT1 8 4
- * all other formats 4 *see below"
- *
- * "- align_j = 4 for any depth buffer
- * - align_j = 2 for separate stencil buffer
- * - align_j = 4 for any render target surface is multisampled (4x)
- * - align_j = 4 for any render target surface with Surface Vertical
- * Alignment = VALIGN_4
- * - align_j = 2 for any render target surface with Surface Vertical
- * Alignment = VALIGN_2
- * - align_j = 2 for all other render target surface
- * - align_j = 2 for any sampling engine surface with Surface Vertical
- * Alignment = VALIGN_2
- * - align_j = 4 for any sampling engine surface with Surface Vertical
- * Alignment = VALIGN_4"
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 86:
- *
- * "This field (Surface Vertical Alignment) must be set to VALIGN_2 if
- * the Surface Format is 96 bits per element (BPE)."
- *
- * They can be rephrased as
- *
- * align_i align_j
- * compressed formats block width block height
- * GEN6_FORMAT_R8_UINT 4 2
- * other depth/stencil formats 4 4
- * 4x multisampled 4 4
- * bpp 96 4 2
- * others 4 2 or 4
- */
-
- *align_i = (info->compressed) ? info->block_width : 4;
- if (info->compressed) {
- *align_j = info->block_height;
- } else if (info->bind_zs) {
- *align_j = (info->format == GEN6_FORMAT_R8_UINT) ? 2 : 4;
- } else {
- *align_j = (info->sample_count > 1 || info->block_size != 12) ? 4 : 2;
- }
-}
-
-static void
-image_get_gen7_alignments(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- enum gen_surface_tiling tiling,
- int *align_i, int *align_j)
-{
- int i, j;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 1 part 1, page 110:
- *
- * "surface defined by surface format align_i align_j
- * 3DSTATE_DEPTH_BUFFER D16_UNORM 8 4
- * not D16_UNORM 4 4
- * 3DSTATE_STENCIL_BUFFER N/A 8 8
- * SURFACE_STATE BC*, ETC*, EAC* 4 4
- * FXT1 8 4
- * all others (set by SURFACE_STATE)"
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 63:
- *
- * "- This field (Surface Vertical Aligment) is intended to be set to
- * VALIGN_4 if the surface was rendered as a depth buffer, for a
- * multisampled (4x) render target, or for a multisampled (8x)
- * render target, since these surfaces support only alignment of 4.
- * - Use of VALIGN_4 for other surfaces is supported, but uses more
- * memory.
- * - This field must be set to VALIGN_4 for all tiled Y Render Target
- * surfaces.
- * - Value of 1 is not supported for format YCRCB_NORMAL (0x182),
- * YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY (0x190)
- * - If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
- * must be set to VALIGN_4."
- * - VALIGN_4 is not supported for surface format R32G32B32_FLOAT."
- *
- * "- This field (Surface Horizontal Aligment) is intended to be set to
- * HALIGN_8 only if the surface was rendered as a depth buffer with
- * Z16 format or a stencil buffer, since these surfaces support only
- * alignment of 8.
- * - Use of HALIGN_8 for other surfaces is supported, but uses more
- * memory.
- * - This field must be set to HALIGN_4 if the Surface Format is BC*.
- * - This field must be set to HALIGN_8 if the Surface Format is
- * FXT1."
- *
- * They can be rephrased as
- *
- * align_i align_j
- * compressed formats block width block height
- * GEN6_FORMAT_R16_UNORM 8 4
- * GEN6_FORMAT_R8_UINT 8 8
- * other depth/stencil formats 4 4
- * 2x or 4x multisampled 4 or 8 4
- * tiled Y 4 or 8 4 (if rt)
- * GEN6_FORMAT_R32G32B32_FLOAT 4 or 8 2
- * others 4 or 8 2 or 4
- */
- if (info->compressed) {
- i = info->block_width;
- j = info->block_height;
- } else if (info->bind_zs) {
- switch (info->format) {
- case GEN6_FORMAT_R16_UNORM:
- i = 8;
- j = 4;
- break;
- case GEN6_FORMAT_R8_UINT:
- i = 8;
- j = 8;
- break;
- default:
- i = 4;
- j = 4;
- break;
- }
- } else {
- const bool valign_4 =
- (info->sample_count > 1 || ilo_dev_gen(dev) >= ILO_GEN(8) ||
- (tiling == GEN6_TILING_Y && info->bind_surface_dp_render));
-
- if (ilo_dev_gen(dev) < ILO_GEN(8) && valign_4)
- assert(info->format != GEN6_FORMAT_R32G32B32_FLOAT);
-
- i = 4;
- j = (valign_4) ? 4 : 2;
- }
-
- *align_i = i;
- *align_j = j;
-}
-
-static bool
-image_init_gen6_hardware_layout(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- layout->walk = image_get_gen7_walk(dev, info);
- else
- layout->walk = image_get_gen6_walk(dev, info);
-
- layout->interleaved_samples =
- image_get_gen6_interleaved_samples(dev, info);
-
- layout->valid_tilings = image_get_gen6_valid_tilings(dev, info);
- if (!layout->valid_tilings)
- return false;
-
- layout->tiling = image_get_gen6_tiling(dev, info, layout->valid_tilings);
-
- if (image_get_gen6_hiz_enable(dev, info))
- layout->aux = ILO_IMAGE_AUX_HIZ;
- else if (ilo_dev_gen(dev) >= ILO_GEN(7) &&
- image_get_gen7_mcs_enable(dev, info, layout->tiling))
- layout->aux = ILO_IMAGE_AUX_MCS;
- else
- layout->aux = ILO_IMAGE_AUX_NONE;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- image_get_gen7_alignments(dev, info, layout->tiling,
- &layout->align_i, &layout->align_j);
- } else {
- image_get_gen6_alignments(dev, info,
- &layout->align_i, &layout->align_j);
- }
-
- return true;
-}
-
-static bool
-image_init_gen6_transfer_layout(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* we can define our own layout to save space */
- layout->walk = ILO_IMAGE_WALK_LOD;
- layout->interleaved_samples = false;
- layout->valid_tilings = IMAGE_TILING_NONE;
- layout->tiling = GEN6_TILING_NONE;
- layout->aux = ILO_IMAGE_AUX_NONE;
- layout->align_i = info->block_width;
- layout->align_j = info->block_height;
-
- return true;
-}
-
-static void
-image_get_gen6_slice_size(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- const struct ilo_image_layout *layout,
- uint8_t level,
- int *width, int *height)
-{
- int w, h;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- w = u_minify(info->width, level);
- h = u_minify(info->height, level);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 114:
- *
- * "The dimensions of the mip maps are first determined by applying the
- * sizing algorithm presented in Non-Power-of-Two Mipmaps above. Then,
- * if necessary, they are padded out to compression block boundaries."
- */
- w = align(w, info->block_width);
- h = align(h, info->block_height);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 111:
- *
- * "If the surface is multisampled (4x), these values must be adjusted
- * as follows before proceeding:
- *
- * W_L = ceiling(W_L / 2) * 4
- * H_L = ceiling(H_L / 2) * 4"
- *
- * From the Ivy Bridge PRM, volume 1 part 1, page 108:
- *
- * "If the surface is multisampled and it is a depth or stencil surface
- * or Multisampled Surface StorageFormat in SURFACE_STATE is
- * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
- * proceeding:
- *
- * #samples W_L = H_L =
- * 2 ceiling(W_L / 2) * 4 HL [no adjustment]
- * 4 ceiling(W_L / 2) * 4 ceiling(H_L / 2) * 4
- * 8 ceiling(W_L / 2) * 8 ceiling(H_L / 2) * 4
- * 16 ceiling(W_L / 2) * 8 ceiling(H_L / 2) * 8"
- *
- * For interleaved samples (4x), where pixels
- *
- * (x, y ) (x+1, y )
- * (x, y+1) (x+1, y+1)
- *
- * would be is occupied by
- *
- * (x, y , si0) (x+1, y , si0) (x, y , si1) (x+1, y , si1)
- * (x, y+1, si0) (x+1, y+1, si0) (x, y+1, si1) (x+1, y+1, si1)
- * (x, y , si2) (x+1, y , si2) (x, y , si3) (x+1, y , si3)
- * (x, y+1, si2) (x+1, y+1, si2) (x, y+1, si3) (x+1, y+1, si3)
- *
- * Thus the need to
- *
- * w = align(w, 2) * 2;
- * y = align(y, 2) * 2;
- */
- if (layout->interleaved_samples) {
- switch (info->sample_count) {
- case 1:
- break;
- case 2:
- w = align(w, 2) * 2;
- break;
- case 4:
- w = align(w, 2) * 2;
- h = align(h, 2) * 2;
- break;
- case 8:
- w = align(w, 2) * 4;
- h = align(h, 2) * 2;
- break;
- case 16:
- w = align(w, 2) * 4;
- h = align(h, 2) * 4;
- break;
- default:
- assert(!"unsupported sample count");
- break;
- }
- }
-
- /*
- * From the Ivy Bridge PRM, volume 1 part 1, page 108:
- *
- * "For separate stencil buffer, the width must be mutiplied by 2 and
- * height divided by 2..."
- *
- * To make things easier (for transfer), we will just double the stencil
- * stride in 3DSTATE_STENCIL_BUFFER.
- */
- w = align(w, layout->align_i);
- h = align(h, layout->align_j);
-
- *width = w;
- *height = h;
-}
-
-static int
-image_get_gen6_layer_count(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- const struct ilo_image_layout *layout)
-{
- int count = info->array_size;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* samples of the same index are stored in a layer */
- if (!layout->interleaved_samples)
- count *= info->sample_count;
-
- return count;
-}
-
-static void
-image_get_gen6_walk_layer_heights(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- layout->walk_layer_h0 = layout->lods[0].slice_height;
-
- if (info->level_count > 1) {
- layout->walk_layer_h1 = layout->lods[1].slice_height;
- } else {
- int dummy;
- image_get_gen6_slice_size(dev, info, layout, 1,
- &dummy, &layout->walk_layer_h1);
- }
-
- if (image_get_gen6_layer_count(dev, info, layout) == 1) {
- layout->walk_layer_height = 0;
- return;
- }
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 115:
- *
- * "The following equation is used for surface formats other than
- * compressed textures:
- *
- * QPitch = (h0 + h1 + 11j)"
- *
- * "The equation for compressed textures (BC* and FXT1 surface formats)
- * follows:
- *
- * QPitch = (h0 + h1 + 11j) / 4"
- *
- * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the
- * value calculated in the equation above, for every other odd Surface
- * Height starting from 1 i.e. 1,5,9,13"
- *
- * From the Ivy Bridge PRM, volume 1 part 1, page 111-112:
- *
- * "If Surface Array Spacing is set to ARYSPC_FULL (note that the depth
- * buffer and stencil buffer have an implied value of ARYSPC_FULL):
- *
- * QPitch = (h0 + h1 + 12j)
- * QPitch = (h0 + h1 + 12j) / 4 (compressed)
- *
- * (There are many typos or missing words here...)"
- *
- * To access the N-th slice, an offset of (Stride * QPitch * N) is added to
- * the base address. The PRM divides QPitch by 4 for compressed formats
- * because the block height for those formats are 4, and it wants QPitch to
- * mean the number of memory rows, as opposed to texel rows, between
- * slices. Since we use texel rows everywhere, we do not need to divide
- * QPitch by 4.
- */
- layout->walk_layer_height = layout->walk_layer_h0 + layout->walk_layer_h1 +
- ((ilo_dev_gen(dev) >= ILO_GEN(7)) ? 12 : 11) * layout->align_j;
-
- if (ilo_dev_gen(dev) == ILO_GEN(6) && info->sample_count > 1 &&
- info->height % 4 == 1)
- layout->walk_layer_height += 4;
-}
-
-static void
-image_get_gen6_monolithic_size(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout,
- int max_x, int max_y)
-{
- int align_w = 1, align_h = 1, pad_h = 0;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 118:
- *
- * "To determine the necessary padding on the bottom and right side of
- * the surface, refer to the table in Section 7.18.3.4 for the i and j
- * parameters for the surface format in use. The surface must then be
- * extended to the next multiple of the alignment unit size in each
- * dimension, and all texels contained in this extended surface must
- * have valid GTT entries."
- *
- * "For cube surfaces, an additional two rows of padding are required
- * at the bottom of the surface. This must be ensured regardless of
- * whether the surface is stored tiled or linear. This is due to the
- * potential rotation of cache line orientation from memory to cache."
- *
- * "For compressed textures (BC* and FXT1 surface formats), padding at
- * the bottom of the surface is to an even compressed row, which is
- * equal to a multiple of 8 uncompressed texel rows. Thus, for padding
- * purposes, these surfaces behave as if j = 8 only for surface
- * padding purposes. The value of 4 for j still applies for mip level
- * alignment and QPitch calculation."
- */
- if (info->bind_surface_sampler) {
- align_w = MAX2(align_w, layout->align_i);
- align_h = MAX2(align_h, layout->align_j);
-
- if (info->type == GEN6_SURFTYPE_CUBE)
- pad_h += 2;
-
- if (info->compressed)
- align_h = MAX2(align_h, layout->align_j * 2);
- }
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 118:
- *
- * "If the surface contains an odd number of rows of data, a final row
- * below the surface must be allocated."
- */
- if (info->bind_surface_dp_render)
- align_h = MAX2(align_h, 2);
-
- /*
- * Depth Buffer Clear/Resolve works in 8x4 sample blocks. Pad to allow HiZ
- * for unaligned non-mipmapped and non-array images.
- */
- if (layout->aux == ILO_IMAGE_AUX_HIZ &&
- info->level_count == 1 && info->array_size == 1 && info->depth == 1) {
- align_w = MAX2(align_w, 8);
- align_h = MAX2(align_h, 4);
- }
-
- layout->monolithic_width = align(max_x, align_w);
- layout->monolithic_height = align(max_y + pad_h, align_h);
-}
-
-static void
-image_get_gen6_lods(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout)
-{
- const int layer_count = image_get_gen6_layer_count(dev, info, layout);
- int cur_x, cur_y, max_x, max_y;
- uint8_t lv;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- cur_x = 0;
- cur_y = 0;
- max_x = 0;
- max_y = 0;
- for (lv = 0; lv < info->level_count; lv++) {
- int slice_w, slice_h, lod_w, lod_h;
-
- image_get_gen6_slice_size(dev, info, layout, lv, &slice_w, &slice_h);
-
- layout->lods[lv].x = cur_x;
- layout->lods[lv].y = cur_y;
- layout->lods[lv].slice_width = slice_w;
- layout->lods[lv].slice_height = slice_h;
-
- switch (layout->walk) {
- case ILO_IMAGE_WALK_LAYER:
- lod_w = slice_w;
- lod_h = slice_h;
-
- /* MIPLAYOUT_BELOW */
- if (lv == 1)
- cur_x += lod_w;
- else
- cur_y += lod_h;
- break;
- case ILO_IMAGE_WALK_LOD:
- lod_w = slice_w;
- lod_h = slice_h * layer_count;
-
- if (lv == 1)
- cur_x += lod_w;
- else
- cur_y += lod_h;
-
- /* every LOD begins at tile boundaries */
- if (info->level_count > 1) {
- assert(info->format == GEN6_FORMAT_R8_UINT);
- cur_x = align(cur_x, 64);
- cur_y = align(cur_y, 64);
- }
- break;
- case ILO_IMAGE_WALK_3D:
- {
- const int slice_count = u_minify(info->depth, lv);
- const int slice_count_per_row = 1 << lv;
- const int row_count =
- (slice_count + slice_count_per_row - 1) / slice_count_per_row;
-
- lod_w = slice_w * slice_count_per_row;
- lod_h = slice_h * row_count;
- }
-
- cur_y += lod_h;
- break;
- default:
- assert(!"unknown walk type");
- lod_w = 0;
- lod_h = 0;
- break;
- }
-
- if (max_x < layout->lods[lv].x + lod_w)
- max_x = layout->lods[lv].x + lod_w;
- if (max_y < layout->lods[lv].y + lod_h)
- max_y = layout->lods[lv].y + lod_h;
- }
-
- if (layout->walk == ILO_IMAGE_WALK_LAYER) {
- image_get_gen6_walk_layer_heights(dev, info, layout);
- if (layer_count > 1)
- max_y += layout->walk_layer_height * (layer_count - 1);
- } else {
- layout->walk_layer_h0 = 0;
- layout->walk_layer_h1 = 0;
- layout->walk_layer_height = 0;
- }
-
- image_get_gen6_monolithic_size(dev, info, layout, max_x, max_y);
-}
-
-static bool
-image_bind_gpu(const struct ilo_image_info *info)
-{
- return (info->bind_surface_sampler ||
- info->bind_surface_dp_render ||
- info->bind_surface_dp_typed ||
- info->bind_zs ||
- info->bind_scanout ||
- info->bind_cursor);
-}
-
-static bool
-image_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 314:
- *
- * "The separate stencil buffer is always enabled, thus the field in
- * 3DSTATE_DEPTH_BUFFER to explicitly enable the separate stencil
- * buffer has been removed Surface formats with interleaved depth and
- * stencil are no longer supported"
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && info->bind_zs)
- assert(!info->interleaved_stencil);
-
- return true;
-}
-
-static bool
-image_get_gen6_layout(const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- struct ilo_image_layout *layout)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!image_validate_gen6(dev, info))
- return false;
-
- if (image_bind_gpu(info) || info->level_count > 1) {
- if (!image_init_gen6_hardware_layout(dev, info, layout))
- return false;
- } else {
- if (!image_init_gen6_transfer_layout(dev, info, layout))
- return false;
- }
-
- /*
- * the fact that align i and j are multiples of block width and height
- * respectively is what makes the size of the bo a multiple of the block
- * size, slices start at block boundaries, and many of the computations
- * work.
- */
- assert(layout->align_i % info->block_width == 0);
- assert(layout->align_j % info->block_height == 0);
-
- /* make sure align() works */
- assert(util_is_power_of_two(layout->align_i) &&
- util_is_power_of_two(layout->align_j));
- assert(util_is_power_of_two(info->block_width) &&
- util_is_power_of_two(info->block_height));
-
- image_get_gen6_lods(dev, info, layout);
-
- assert(layout->walk_layer_height % info->block_height == 0);
- assert(layout->monolithic_width % info->block_width == 0);
- assert(layout->monolithic_height % info->block_height == 0);
-
- return true;
-}
-
-static bool
-image_set_gen6_bo_size(struct ilo_image *img,
- const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- const struct ilo_image_layout *layout)
-{
- int stride, height;
- int align_w, align_h;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- stride = (layout->monolithic_width / info->block_width) * info->block_size;
- height = layout->monolithic_height / info->block_height;
-
- /*
- * From the Haswell PRM, volume 5, page 163:
- *
- * "For linear surfaces, additional padding of 64 bytes is required
- * at the bottom of the surface. This is in addition to the padding
- * required above."
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && info->bind_surface_sampler &&
- layout->tiling == GEN6_TILING_NONE)
- height += (64 + stride - 1) / stride;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 81:
- *
- * "- For linear render target surfaces, the pitch must be a multiple
- * of the element size for non-YUV surface formats. Pitch must be a
- * multiple of 2 * element size for YUV surface formats.
- *
- * - For other linear surfaces, the pitch can be any multiple of
- * bytes.
- * - For tiled surfaces, the pitch must be a multiple of the tile
- * width."
- *
- * Different requirements may exist when the image is used in different
- * places, but our alignments here should be good enough that we do not
- * need to check info->bind_x.
- */
- switch (layout->tiling) {
- case GEN6_TILING_X:
- align_w = 512;
- align_h = 8;
- break;
- case GEN6_TILING_Y:
- align_w = 128;
- align_h = 32;
- break;
- case GEN8_TILING_W:
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 22:
- *
- * "A 4KB tile is subdivided into 8-high by 8-wide array of
- * Blocks for W-Major Tiles (W Tiles). Each Block is 8 rows by 8
- * bytes."
- */
- align_w = 64;
- align_h = 64;
- break;
- default:
- assert(layout->tiling == GEN6_TILING_NONE);
- /* some good enough values */
- align_w = 64;
- align_h = 2;
- break;
- }
-
- if (info->force_bo_stride) {
- if (info->force_bo_stride % align_w || info->force_bo_stride < stride)
- return false;
-
- img->bo_stride = info->force_bo_stride;
- } else {
- img->bo_stride = align(stride, align_w);
- }
-
- img->bo_height = align(height, align_h);
-
- return true;
-}
-
-static bool
-image_set_gen6_hiz(struct ilo_image *img,
- const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- const struct ilo_image_layout *layout)
-{
- const int hz_align_j = 8;
- enum ilo_image_walk_type hz_walk;
- int hz_width, hz_height;
- int hz_clear_w, hz_clear_h;
- uint8_t lv;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(layout->aux == ILO_IMAGE_AUX_HIZ);
-
- assert(layout->walk == ILO_IMAGE_WALK_LAYER ||
- layout->walk == ILO_IMAGE_WALK_3D);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 312:
- *
- * "The hierarchical depth buffer does not support the LOD field, it is
- * assumed by hardware to be zero. A separate hierarachical depth
- * buffer is required for each LOD used, and the corresponding
- * buffer's state delivered to hardware each time a new depth buffer
- * state with modified LOD is delivered."
- *
- * We will put all LODs in a single bo with ILO_IMAGE_WALK_LOD.
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- hz_walk = layout->walk;
- else
- hz_walk = ILO_IMAGE_WALK_LOD;
-
- /*
- * See the Sandy Bridge PRM, volume 2 part 1, page 312, and the Ivy Bridge
- * PRM, volume 2 part 1, page 312-313.
- *
- * It seems HiZ buffer is aligned to 8x8, with every two rows packed into a
- * memory row.
- */
- switch (hz_walk) {
- case ILO_IMAGE_WALK_LAYER:
- {
- const int h0 = align(layout->walk_layer_h0, hz_align_j);
- const int h1 = align(layout->walk_layer_h1, hz_align_j);
- const int htail =
- ((ilo_dev_gen(dev) >= ILO_GEN(7)) ? 12 : 11) * hz_align_j;
- const int hz_qpitch = h0 + h1 + htail;
-
- hz_width = align(layout->lods[0].slice_width, 16);
-
- hz_height = hz_qpitch * info->array_size / 2;
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- hz_height = align(hz_height, 8);
-
- img->aux.walk_layer_height = hz_qpitch;
- }
- break;
- case ILO_IMAGE_WALK_LOD:
- {
- int lod_tx[ILO_IMAGE_MAX_LEVEL_COUNT];
- int lod_ty[ILO_IMAGE_MAX_LEVEL_COUNT];
- int cur_tx, cur_ty;
-
- /* figure out the tile offsets of LODs */
- hz_width = 0;
- hz_height = 0;
- cur_tx = 0;
- cur_ty = 0;
- for (lv = 0; lv < info->level_count; lv++) {
- int tw, th;
-
- lod_tx[lv] = cur_tx;
- lod_ty[lv] = cur_ty;
-
- tw = align(layout->lods[lv].slice_width, 16);
- th = align(layout->lods[lv].slice_height, hz_align_j) *
- info->array_size / 2;
- /* convert to Y-tiles */
- tw = (tw + 127) / 128;
- th = (th + 31) / 32;
-
- if (hz_width < cur_tx + tw)
- hz_width = cur_tx + tw;
- if (hz_height < cur_ty + th)
- hz_height = cur_ty + th;
-
- if (lv == 1)
- cur_tx += tw;
- else
- cur_ty += th;
- }
-
- /* convert tile offsets to memory offsets */
- for (lv = 0; lv < info->level_count; lv++) {
- img->aux.walk_lod_offsets[lv] =
- (lod_ty[lv] * hz_width + lod_tx[lv]) * 4096;
- }
-
- hz_width *= 128;
- hz_height *= 32;
- }
- break;
- case ILO_IMAGE_WALK_3D:
- hz_width = align(layout->lods[0].slice_width, 16);
-
- hz_height = 0;
- for (lv = 0; lv < info->level_count; lv++) {
- const int h = align(layout->lods[lv].slice_height, hz_align_j);
- /* according to the formula, slices are packed together vertically */
- hz_height += h * u_minify(info->depth, lv);
- }
- hz_height /= 2;
- break;
- default:
- assert(!"unknown HiZ walk");
- hz_width = 0;
- hz_height = 0;
- break;
- }
-
- /*
- * In hiz_align_fb(), we will align the LODs to 8x4 sample blocks.
- * Experiments on Haswell show that aligning the RECTLIST primitive and
- * 3DSTATE_DRAWING_RECTANGLE alone are not enough. The LOD sizes must be
- * aligned.
- */
- hz_clear_w = 8;
- hz_clear_h = 4;
- switch (info->sample_count) {
- case 1:
- default:
- break;
- case 2:
- hz_clear_w /= 2;
- break;
- case 4:
- hz_clear_w /= 2;
- hz_clear_h /= 2;
- break;
- case 8:
- hz_clear_w /= 4;
- hz_clear_h /= 2;
- break;
- case 16:
- hz_clear_w /= 4;
- hz_clear_h /= 4;
- break;
- }
-
- for (lv = 0; lv < info->level_count; lv++) {
- if (u_minify(info->width, lv) % hz_clear_w ||
- u_minify(info->height, lv) % hz_clear_h)
- break;
- img->aux.enables |= 1 << lv;
- }
-
- /* we padded to allow this in image_get_gen6_monolithic_size() */
- if (info->level_count == 1 && info->array_size == 1 && info->depth == 1)
- img->aux.enables |= 0x1;
-
- /* align to Y-tile */
- img->aux.bo_stride = align(hz_width, 128);
- img->aux.bo_height = align(hz_height, 32);
-
- return true;
-}
-
-static bool
-image_set_gen7_mcs(struct ilo_image *img,
- const struct ilo_dev *dev,
- const struct ilo_image_info *info,
- const struct ilo_image_layout *layout)
-{
- int mcs_width, mcs_height, mcs_cpp;
- int downscale_x, downscale_y;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- assert(layout->aux == ILO_IMAGE_AUX_MCS);
-
- if (info->sample_count > 1) {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 326, the clear
- * rectangle is scaled down by 8x2 for 4X MSAA and 2x2 for 8X MSAA. The
- * need of scale down could be that the clear rectangle is used to clear
- * the MCS instead of the RT.
- *
- * For 8X MSAA, we need 32 bits in MCS for every pixel in the RT. The
- * 2x2 factor could come from that the hardware writes 128 bits (an
- * OWord) at a time, and the OWord in MCS maps to a 2x2 pixel block in
- * the RT. For 4X MSAA, we need 8 bits in MCS for every pixel in the
- * RT. Similarly, we could reason that an OWord in 4X MCS maps to a 8x2
- * pixel block in the RT.
- */
- switch (info->sample_count) {
- case 2:
- case 4:
- downscale_x = 8;
- downscale_y = 2;
- mcs_cpp = 1;
- break;
- case 8:
- downscale_x = 2;
- downscale_y = 2;
- mcs_cpp = 4;
- break;
- case 16:
- downscale_x = 2;
- downscale_y = 1;
- mcs_cpp = 8;
- break;
- default:
- assert(!"unsupported sample count");
- return false;
- break;
- }
-
- /*
- * It also appears that the 2x2 subspans generated by the scaled-down
- * clear rectangle cannot be masked. The scale-down clear rectangle
- * thus must be aligned to 2x2, and we need to pad.
- */
- mcs_width = align(info->width, downscale_x * 2);
- mcs_height = align(info->height, downscale_y * 2);
- } else {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 327:
- *
- * " Pixels Lines
- * TiledY RT CL
- * bpp
- * 32 8 4
- * 64 4 4
- * 128 2 4
- *
- * TiledX RT CL
- * bpp
- * 32 16 2
- * 64 8 2
- * 128 4 2"
- *
- * This table and the two following tables define the RT alignments, the
- * clear rectangle alignments, and the clear rectangle scale factors.
- * Viewing the RT alignments as the sizes of 128-byte blocks, we can see
- * that the clear rectangle alignments are 16x32 blocks, and the clear
- * rectangle scale factors are 8x16 blocks.
- *
- * For non-MSAA RT, we need 1 bit in MCS for every 128-byte block in the
- * RT. Similar to the MSAA cases, we can argue that an OWord maps to
- * 8x16 blocks.
- *
- * One problem with this reasoning is that a Y-tile in MCS has 8x32
- * OWords and maps to 64x512 128-byte blocks. This differs from i965,
- * which says that a Y-tile maps to 128x256 blocks (\see
- * intel_get_non_msrt_mcs_alignment). It does not really change
- * anything except for the size of the allocated MCS. Let's see if we
- * hit out-of-bound access.
- */
- switch (layout->tiling) {
- case GEN6_TILING_X:
- downscale_x = 64 / info->block_size;
- downscale_y = 2;
- break;
- case GEN6_TILING_Y:
- downscale_x = 32 / info->block_size;
- downscale_y = 4;
- break;
- default:
- assert(!"unsupported tiling mode");
- return false;
- break;
- }
-
- downscale_x *= 8;
- downscale_y *= 16;
-
- /*
- * From the Haswell PRM, volume 7, page 652:
- *
- * "Clear rectangle must be aligned to two times the number of
- * pixels in the table shown below due to 16X16 hashing across the
- * slice."
- *
- * The scaled-down clear rectangle must be aligned to 4x4 instead of
- * 2x2, and we need to pad.
- */
- mcs_width = align(info->width, downscale_x * 4) / downscale_x;
- mcs_height = align(info->height, downscale_y * 4) / downscale_y;
- mcs_cpp = 16; /* an OWord */
- }
-
- img->aux.enables = (1 << info->level_count) - 1;
- /* align to Y-tile */
- img->aux.bo_stride = align(mcs_width * mcs_cpp, 128);
- img->aux.bo_height = align(mcs_height, 32);
-
- return true;
-}
-
-bool
-ilo_image_init(struct ilo_image *img,
- const struct ilo_dev *dev,
- const struct ilo_image_info *info)
-{
- struct ilo_image_layout layout;
-
- assert(ilo_is_zeroed(img, sizeof(*img)));
-
- memset(&layout, 0, sizeof(layout));
- layout.lods = img->lods;
-
- if (!image_get_gen6_layout(dev, info, &layout))
- return false;
-
- img->type = info->type;
-
- img->format = info->format;
- img->block_width = info->block_width;
- img->block_height = info->block_height;
- img->block_size = info->block_size;
-
- img->width0 = info->width;
- img->height0 = info->height;
- img->depth0 = info->depth;
- img->array_size = info->array_size;
- img->level_count = info->level_count;
- img->sample_count = info->sample_count;
-
- img->walk = layout.walk;
- img->interleaved_samples = layout.interleaved_samples;
-
- img->tiling = layout.tiling;
-
- img->aux.type = layout.aux;
-
- img->align_i = layout.align_i;
- img->align_j = layout.align_j;
-
- img->walk_layer_height = layout.walk_layer_height;
-
- if (!image_set_gen6_bo_size(img, dev, info, &layout))
- return false;
-
- img->scanout = info->bind_scanout;
-
- switch (layout.aux) {
- case ILO_IMAGE_AUX_HIZ:
- image_set_gen6_hiz(img, dev, info, &layout);
- break;
- case ILO_IMAGE_AUX_MCS:
- image_set_gen7_mcs(img, dev, info, &layout);
- break;
- default:
- break;
- }
-
- return true;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_image.h b/src/gallium/drivers/ilo/core/ilo_image.h
deleted file mode 100644
index 546e0ff7739..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_image.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2014 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_IMAGE_H
-#define ILO_IMAGE_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Ivy Bridge PRM, volume 4 part 1, page 75:
- *
- * "(MIP Count / LOD) representing [1,15] MIP levels"
- */
-#define ILO_IMAGE_MAX_LEVEL_COUNT 15
-
-enum ilo_image_aux_type {
- ILO_IMAGE_AUX_NONE,
- ILO_IMAGE_AUX_HIZ,
- ILO_IMAGE_AUX_MCS,
-};
-
-enum ilo_image_walk_type {
- /*
- * LODs of each array layer are first packed together in MIPLAYOUT_BELOW.
- * Array layers are then stacked together vertically.
- *
- * This can be used for mipmapped 2D textures.
- */
- ILO_IMAGE_WALK_LAYER,
-
- /*
- * Array layers of each LOD are first stacked together vertically and
- * tightly. LODs are then packed together in MIPLAYOUT_BELOW with each LOD
- * starting at page boundaries.
- *
- * This is usually used for non-mipmapped 2D textures, as multiple LODs are
- * not supported natively.
- */
- ILO_IMAGE_WALK_LOD,
-
- /*
- * 3D slices of each LOD are first packed together horizontally and tightly
- * with wrapping. LODs are then stacked together vertically and tightly.
- *
- * This is used for 3D textures.
- */
- ILO_IMAGE_WALK_3D,
-};
-
-struct ilo_image_info {
- enum gen_surface_type type;
-
- enum gen_surface_format format;
- bool interleaved_stencil;
- bool is_integer;
- /* width, height and size of pixel blocks */
- bool compressed;
- unsigned block_width;
- unsigned block_height;
- unsigned block_size;
-
- /* image size */
- uint16_t width;
- uint16_t height;
- uint16_t depth;
- uint16_t array_size;
- uint8_t level_count;
- uint8_t sample_count;
-
- /* disable optional aux */
- bool aux_disable;
-
- /* tilings to consider, if any bit is set */
- uint8_t valid_tilings;
-
- /*
- * prefer GEN6_TILING_NONE when the (estimated) image size exceeds the
- * threshold; ignored when zero
- */
- uint32_t prefer_linear_threshold;
-
- /* force a stride when non-zero */
- uint32_t force_bo_stride;
-
- bool bind_surface_sampler;
- bool bind_surface_dp_render;
- bool bind_surface_dp_typed;
- bool bind_zs;
- bool bind_scanout;
- bool bind_cursor;
-};
-
-/*
- * When the walk type is ILO_IMAGE_WALK_LAYER, there is only a slice in each
- * LOD and this is used to describe LODs in the first array layer. Otherwise,
- * there can be multiple slices in each LOD and this is used to describe the
- * first slice in each LOD.
- */
-struct ilo_image_lod {
- /* physical position in pixels */
- unsigned x;
- unsigned y;
-
- /* physical size of a slice in pixels */
- unsigned slice_width;
- unsigned slice_height;
-};
-
-/**
- * Texture layout.
- */
-struct ilo_image {
- enum gen_surface_type type;
-
- enum gen_surface_format format;
- bool interleaved_stencil;
-
- /* size, format, etc for programming hardware states */
- unsigned width0;
- unsigned height0;
- unsigned depth0;
- unsigned array_size;
- unsigned level_count;
- unsigned sample_count;
-
- /*
- * width, height, and size of pixel blocks for conversion between pixel
- * positions and memory offsets
- */
- unsigned block_width;
- unsigned block_height;
- unsigned block_size;
-
- enum ilo_image_walk_type walk;
- bool interleaved_samples;
-
- enum gen_surface_tiling tiling;
-
- /* physical LOD slice alignments */
- unsigned align_i;
- unsigned align_j;
-
- struct ilo_image_lod lods[ILO_IMAGE_MAX_LEVEL_COUNT];
-
- /* physical layer height for ILO_IMAGE_WALK_LAYER */
- unsigned walk_layer_height;
-
- /* distance in bytes between two pixel block rows */
- unsigned bo_stride;
- /* number of pixel block rows */
- unsigned bo_height;
-
- bool scanout;
-
- struct {
- enum ilo_image_aux_type type;
-
- /* bitmask of levels that can use aux */
- unsigned enables;
-
- /* LOD offsets for ILO_IMAGE_WALK_LOD */
- unsigned walk_lod_offsets[ILO_IMAGE_MAX_LEVEL_COUNT];
-
- unsigned walk_layer_height;
- unsigned bo_stride;
- unsigned bo_height;
- } aux;
-};
-
-bool
-ilo_image_init(struct ilo_image *img,
- const struct ilo_dev *dev,
- const struct ilo_image_info *info);
-
-static inline bool
-ilo_image_can_enable_aux(const struct ilo_image *img, unsigned level)
-{
- return (img->aux.enables & (1 << level));
-}
-
-/**
- * Convert from pixel position to 2D memory offset.
- */
-static inline void
-ilo_image_pos_to_mem(const struct ilo_image *img,
- unsigned pos_x, unsigned pos_y,
- unsigned *mem_x, unsigned *mem_y)
-{
- assert(pos_x % img->block_width == 0);
- assert(pos_y % img->block_height == 0);
-
- *mem_x = pos_x / img->block_width * img->block_size;
- *mem_y = pos_y / img->block_height;
-}
-
-/**
- * Convert from 2D memory offset to linear offset.
- */
-static inline unsigned
-ilo_image_mem_to_linear(const struct ilo_image *img,
- unsigned mem_x, unsigned mem_y)
-{
- return mem_y * img->bo_stride + mem_x;
-}
-
-/**
- * Convert from 2D memory offset to raw offset.
- */
-static inline unsigned
-ilo_image_mem_to_raw(const struct ilo_image *img,
- unsigned mem_x, unsigned mem_y)
-{
- unsigned tile_w, tile_h;
-
- switch (img->tiling) {
- case GEN6_TILING_NONE:
- tile_w = 1;
- tile_h = 1;
- break;
- case GEN6_TILING_X:
- tile_w = 512;
- tile_h = 8;
- break;
- case GEN6_TILING_Y:
- tile_w = 128;
- tile_h = 32;
- break;
- case GEN8_TILING_W:
- tile_w = 64;
- tile_h = 64;
- break;
- default:
- assert(!"unknown tiling");
- tile_w = 1;
- tile_h = 1;
- break;
- }
-
- assert(mem_x % tile_w == 0);
- assert(mem_y % tile_h == 0);
-
- return mem_y * img->bo_stride + mem_x * tile_h;
-}
-
-/**
- * Return the stride, in bytes, between slices within a level.
- */
-static inline unsigned
-ilo_image_get_slice_stride(const struct ilo_image *img, unsigned level)
-{
- unsigned h;
-
- switch (img->walk) {
- case ILO_IMAGE_WALK_LAYER:
- h = img->walk_layer_height;
- break;
- case ILO_IMAGE_WALK_LOD:
- h = img->lods[level].slice_height;
- break;
- case ILO_IMAGE_WALK_3D:
- if (level == 0) {
- h = img->lods[0].slice_height;
- break;
- }
- /* fall through */
- default:
- assert(!"no single stride to walk across slices");
- h = 0;
- break;
- }
-
- assert(h % img->block_height == 0);
-
- return (h / img->block_height) * img->bo_stride;
-}
-
-/**
- * Return the physical size, in bytes, of a slice in a level.
- */
-static inline unsigned
-ilo_image_get_slice_size(const struct ilo_image *img, unsigned level)
-{
- const unsigned w = img->lods[level].slice_width;
- const unsigned h = img->lods[level].slice_height;
-
- assert(w % img->block_width == 0);
- assert(h % img->block_height == 0);
-
- return (w / img->block_width * img->block_size) *
- (h / img->block_height);
-}
-
-/**
- * Return the pixel position of a slice.
- */
-static inline void
-ilo_image_get_slice_pos(const struct ilo_image *img,
- unsigned level, unsigned slice,
- unsigned *x, unsigned *y)
-{
- switch (img->walk) {
- case ILO_IMAGE_WALK_LAYER:
- *x = img->lods[level].x;
- *y = img->lods[level].y + img->walk_layer_height * slice;
- break;
- case ILO_IMAGE_WALK_LOD:
- *x = img->lods[level].x;
- *y = img->lods[level].y + img->lods[level].slice_height * slice;
- break;
- case ILO_IMAGE_WALK_3D:
- {
- /* slices are packed horizontally with wrapping */
- const unsigned sx = slice & ((1 << level) - 1);
- const unsigned sy = slice >> level;
-
- assert(slice < u_minify(img->depth0, level));
-
- *x = img->lods[level].x + img->lods[level].slice_width * sx;
- *y = img->lods[level].y + img->lods[level].slice_height * sy;
- }
- break;
- default:
- assert(!"unknown img walk type");
- *x = 0;
- *y = 0;
- break;
- }
-
- /* should not exceed the bo size */
- assert(*y + img->lods[level].slice_height <=
- img->bo_height * img->block_height);
-}
-
-#endif /* ILO_IMAGE_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_state_cc.c b/src/gallium/drivers/ilo/core/ilo_state_cc.c
deleted file mode 100644
index 1f2456e19ea..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_cc.c
+++ /dev/null
@@ -1,890 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_cc.h"
-
-static bool
-cc_validate_gen6_stencil(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_stencil_info *stencil = &info->stencil;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 359:
- *
- * "If the Depth Buffer is either undefined or does not have a surface
- * format of D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT and separate
- * stencil buffer is disabled, Stencil Test Enable must be DISABLED"
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 370:
- *
- * "This field (Stencil Test Enable) cannot be enabled if Surface
- * Format in 3DSTATE_DEPTH_BUFFER is set to D16_UNORM."
- */
- if (stencil->test_enable)
- assert(stencil->cv_has_buffer);
-
- return true;
-}
-
-static bool
-cc_validate_gen6_depth(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_depth_info *depth = &info->depth;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 360:
- *
- * "Enabling the Depth Test function without defining a Depth Buffer is
- * UNDEFINED."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 375:
- *
- * "A Depth Buffer must be defined before enabling writes to it, or
- * operation is UNDEFINED."
- */
- if (depth->test_enable || depth->write_enable)
- assert(depth->cv_has_buffer);
-
- return true;
-}
-
-static bool
-cc_set_gen6_DEPTH_STENCIL_STATE(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_stencil_info *stencil = &info->stencil;
- const struct ilo_state_cc_depth_info *depth = &info->depth;
- const struct ilo_state_cc_params_info *params = &info->params;
- uint32_t dw0, dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 6, 7.5);
-
- if (!cc_validate_gen6_stencil(dev, info) ||
- !cc_validate_gen6_depth(dev, info))
- return false;
-
- dw0 = 0;
- dw1 = 0;
- if (stencil->test_enable) {
- const struct ilo_state_cc_stencil_op_info *front = &stencil->front;
- const struct ilo_state_cc_stencil_params_info *front_p =
- &params->stencil_front;
- const struct ilo_state_cc_stencil_op_info *back;
- const struct ilo_state_cc_stencil_params_info *back_p;
-
- dw0 |= GEN6_ZS_DW0_STENCIL_TEST_ENABLE;
-
- if (stencil->twosided_enable) {
- dw0 |= GEN6_ZS_DW0_STENCIL1_ENABLE;
-
- back = &stencil->back;
- back_p = &params->stencil_back;
- } else {
- back = &stencil->front;
- back_p = &params->stencil_front;
- }
-
- dw0 |= front->test_func << GEN6_ZS_DW0_STENCIL_FUNC__SHIFT |
- front->fail_op << GEN6_ZS_DW0_STENCIL_FAIL_OP__SHIFT |
- front->zfail_op << GEN6_ZS_DW0_STENCIL_ZFAIL_OP__SHIFT |
- front->zpass_op << GEN6_ZS_DW0_STENCIL_ZPASS_OP__SHIFT |
- back->test_func << GEN6_ZS_DW0_STENCIL1_FUNC__SHIFT |
- back->fail_op << GEN6_ZS_DW0_STENCIL1_FAIL_OP__SHIFT |
- back->zfail_op << GEN6_ZS_DW0_STENCIL1_ZFAIL_OP__SHIFT |
- back->zpass_op << GEN6_ZS_DW0_STENCIL1_ZPASS_OP__SHIFT;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 363:
- *
- * "If this field (Stencil Buffer Write Enable) is enabled, Stencil
- * Test Enable must also be enabled."
- *
- * This is different from depth write enable, which is independent from
- * depth test enable.
- */
- if (front_p->write_mask || back_p->write_mask)
- dw0 |= GEN6_ZS_DW0_STENCIL_WRITE_ENABLE;
-
- dw1 |= front_p->test_mask << GEN6_ZS_DW1_STENCIL_TEST_MASK__SHIFT |
- front_p->write_mask << GEN6_ZS_DW1_STENCIL_WRITE_MASK__SHIFT |
- back_p->test_mask << GEN6_ZS_DW1_STENCIL1_TEST_MASK__SHIFT |
- back_p->write_mask << GEN6_ZS_DW1_STENCIL1_WRITE_MASK__SHIFT;
- }
-
- dw2 = 0;
- if (depth->test_enable) {
- dw2 |= GEN6_ZS_DW2_DEPTH_TEST_ENABLE |
- depth->test_func << GEN6_ZS_DW2_DEPTH_FUNC__SHIFT;
- } else {
- dw2 |= GEN6_COMPAREFUNCTION_ALWAYS << GEN6_ZS_DW2_DEPTH_FUNC__SHIFT;
- }
-
- /* independent from depth->test_enable */
- if (depth->write_enable)
- dw2 |= GEN6_ZS_DW2_DEPTH_WRITE_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(cc->ds) >= 3);
- cc->ds[0] = dw0;
- cc->ds[1] = dw1;
- cc->ds[2] = dw2;
-
- return true;
-}
-
-static bool
-cc_set_gen8_3DSTATE_WM_DEPTH_STENCIL(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_stencil_info *stencil = &info->stencil;
- const struct ilo_state_cc_depth_info *depth = &info->depth;
- const struct ilo_state_cc_params_info *params = &info->params;
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- if (!cc_validate_gen6_stencil(dev, info) ||
- !cc_validate_gen6_depth(dev, info))
- return false;
-
- dw1 = 0;
- dw2 = 0;
- if (stencil->test_enable) {
- const struct ilo_state_cc_stencil_op_info *front = &stencil->front;
- const struct ilo_state_cc_stencil_params_info *front_p =
- &params->stencil_front;
- const struct ilo_state_cc_stencil_op_info *back;
- const struct ilo_state_cc_stencil_params_info *back_p;
-
- dw1 |= GEN8_ZS_DW1_STENCIL_TEST_ENABLE;
-
- if (stencil->twosided_enable) {
- dw1 |= GEN8_ZS_DW1_STENCIL1_ENABLE;
-
- back = &stencil->back;
- back_p = &params->stencil_back;
- } else {
- back = &stencil->front;
- back_p = &params->stencil_front;
- }
-
- dw1 |= front->fail_op << GEN8_ZS_DW1_STENCIL_FAIL_OP__SHIFT |
- front->zfail_op << GEN8_ZS_DW1_STENCIL_ZFAIL_OP__SHIFT |
- front->zpass_op << GEN8_ZS_DW1_STENCIL_ZPASS_OP__SHIFT |
- back->test_func << GEN8_ZS_DW1_STENCIL1_FUNC__SHIFT |
- back->fail_op << GEN8_ZS_DW1_STENCIL1_FAIL_OP__SHIFT |
- back->zfail_op << GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__SHIFT |
- back->zpass_op << GEN8_ZS_DW1_STENCIL1_ZPASS_OP__SHIFT |
- front->test_func << GEN8_ZS_DW1_STENCIL_FUNC__SHIFT;
-
- if (front_p->write_mask || back_p->write_mask)
- dw1 |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
-
- dw2 |= front_p->test_mask << GEN8_ZS_DW2_STENCIL_TEST_MASK__SHIFT |
- front_p->write_mask << GEN8_ZS_DW2_STENCIL_WRITE_MASK__SHIFT |
- back_p->test_mask << GEN8_ZS_DW2_STENCIL1_TEST_MASK__SHIFT |
- back_p->write_mask << GEN8_ZS_DW2_STENCIL1_WRITE_MASK__SHIFT;
- }
-
- if (depth->test_enable) {
- dw1 |= GEN8_ZS_DW1_DEPTH_TEST_ENABLE |
- depth->test_func << GEN8_ZS_DW1_DEPTH_FUNC__SHIFT;
- } else {
- dw1 |= GEN6_COMPAREFUNCTION_ALWAYS << GEN8_ZS_DW1_DEPTH_FUNC__SHIFT;
- }
-
- if (depth->write_enable)
- dw1 |= GEN8_ZS_DW1_DEPTH_WRITE_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(cc->ds) >= 2);
- cc->ds[0] = dw1;
- cc->ds[1] = dw2;
-
- return true;
-}
-
-static bool
-is_dual_source_blend_factor(enum gen_blend_factor factor)
-{
- switch (factor) {
- case GEN6_BLENDFACTOR_SRC1_COLOR:
- case GEN6_BLENDFACTOR_SRC1_ALPHA:
- case GEN6_BLENDFACTOR_INV_SRC1_COLOR:
- case GEN6_BLENDFACTOR_INV_SRC1_ALPHA:
- return true;
- default:
- return false;
- }
-}
-
-static bool
-cc_get_gen6_dual_source_blending(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_blend_info *blend = &info->blend;
- bool dual_source_blending;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- dual_source_blending = (blend->rt_count &&
- (is_dual_source_blend_factor(blend->rt[0].rgb_src) ||
- is_dual_source_blend_factor(blend->rt[0].rgb_dst) ||
- is_dual_source_blend_factor(blend->rt[0].a_src) ||
- is_dual_source_blend_factor(blend->rt[0].a_dst)));
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 356:
- *
- * "Dual Source Blending: When using "Dual Source" Render Target
- * Write messages, the Source1 pixel color+alpha passed in the
- * message can be selected as a src/dst blend factor. See Color
- * Buffer Blending. In single-source mode, those blend factor
- * selections are invalid. If SRC1 is included in a src/dst blend
- * factor and a DualSource RT Write message is not utilized,
- * results are UNDEFINED. (This reflects the same restriction in DX
- * APIs, where undefined results are produced if "o1" is not
- * written by a PS - there are no default values defined). If SRC1
- * is not included in a src/dst blend factor, dual source blending
- * must be disabled."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 356:
- *
- * "The single source message will not cause a write to the render
- * target if Dual Source Blend Enable in 3DSTATE_WM is enabled."
- *
- * "The dual source message will revert to a single source message
- * using source 0 if Dual Source Blend Enable in 3DSTATE_WM is
- * disabled."
- *
- * Dual source blending must be enabled or disabled universally.
- */
- for (i = 1; i < blend->rt_count; i++) {
- assert(dual_source_blending ==
- (is_dual_source_blend_factor(blend->rt[i].rgb_src) ||
- is_dual_source_blend_factor(blend->rt[i].rgb_dst) ||
- is_dual_source_blend_factor(blend->rt[i].a_src) ||
- is_dual_source_blend_factor(blend->rt[i].a_dst)));
- }
-
- return dual_source_blending;
-}
-
-static bool
-cc_validate_gen6_alpha(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_alpha_info *alpha = &info->alpha;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 356:
- *
- * "Alpha values from the pixel shader are treated as FLOAT32 format
- * for computing the AlphaToCoverage Mask."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 378:
- *
- * "If set (AlphaToCoverage Enable), Source0 Alpha is converted to a
- * temporary 1/2/4-bit coverage mask and the mask bit corresponding to
- * the sample# ANDed with the sample mask bit. If set, sample coverage
- * is computed based on src0 alpha value. Value of 0 disables all
- * samples and value of 1 enables all samples for that pixel. The same
- * coverage needs to apply to all the RTs in MRT case. Further, any
- * value of src0 alpha between 0 and 1 monotonically increases the
- * number of enabled pixels.
- *
- * The same coverage needs to be applied to all the RTs in MRT case."
- *
- * "If set (AlphaToOne Enable), Source0 Alpha is set to 1.0f after
- * (possibly) being used to generate the AlphaToCoverage coverage
- * mask.
- *
- * The same coverage needs to be applied to all the RTs in MRT case.
- *
- * If Dual Source Blending is enabled, this bit must be disabled."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 382:
- *
- * "Alpha Test can only be enabled if Pixel Shader outputs a float
- * alpha value.
- *
- * Alpha Test is applied independently on each render target by
- * comparing that render target's alpha value against the alpha
- * reference value. If the alpha test fails, the corresponding pixel
- * write will be supressed only for that render target. The
- * depth/stencil update will occur if alpha test passes for any render
- * target."
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 194:
- *
- * "Multiple render targets are supported with the single source and
- * replicate data messages. Each render target is accessed with a
- * separate Render Target Write message, each with a different surface
- * indicated (different binding table index). The depth buffer is
- * written only by the message(s) to the last render target, indicated
- * by the Last Render Target Select bit set to clear the pixel
- * scoreboard bits."
- *
- * When AlphaToCoverage/AlphaToOne/AlphaTest is enabled, it is
- * required/desirable for the RT write messages to set "Source0 Alpha
- * Present to RenderTarget" in the MRT case. It is also required/desirable
- * for the alpha values to be FLOAT32.
- */
- if (alpha->alpha_to_coverage || alpha->alpha_to_one || alpha->test_enable)
- assert(alpha->cv_float_source0_alpha);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 356:
- *
- * "[DevSNB]: When NumSamples = 1, AlphaToCoverage and AlphaTo
- * Coverage Dither both must be disabled."
- */
- if (ilo_dev_gen(dev) == ILO_GEN(6) && alpha->alpha_to_coverage)
- assert(alpha->cv_sample_count_one);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 378:
- *
- * "If Dual Source Blending is enabled, this bit (AlphaToOne Enable)
- * must be disabled."
- */
- if (alpha->alpha_to_one)
- assert(!cc_get_gen6_dual_source_blending(dev, info));
-
- return true;
-}
-
-static bool
-cc_validate_gen6_blend(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_blend_info *blend = &info->blend;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(blend->rt_count <= ILO_STATE_CC_BLEND_MAX_RT_COUNT);
-
- return true;
-}
-
-static enum gen_blend_factor
-get_dst_alpha_one_blend_factor(enum gen_blend_factor factor, bool is_rgb)
-{
- switch (factor) {
- case GEN6_BLENDFACTOR_DST_ALPHA:
- return GEN6_BLENDFACTOR_ONE;
- case GEN6_BLENDFACTOR_INV_DST_ALPHA:
- return GEN6_BLENDFACTOR_ZERO;
- case GEN6_BLENDFACTOR_SRC_ALPHA_SATURATE:
- return (is_rgb) ? GEN6_BLENDFACTOR_ZERO : GEN6_BLENDFACTOR_ONE;
- default:
- return factor;
- }
-}
-
-static void
-cc_get_gen6_effective_rt(const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info,
- uint8_t rt_index,
- struct ilo_state_cc_blend_rt_info *dst)
-{
- const struct ilo_state_cc_blend_rt_info *rt = &info->blend.rt[rt_index];
-
- if (rt->logicop_enable || rt->blend_enable ||
- rt->argb_write_disables != 0xf)
- assert(rt->cv_has_buffer);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 365:
- *
- * "Logic Ops are only supported on *_UNORM surfaces (excluding _SRGB
- * variants), otherwise Logic Ops must be DISABLED."
- *
- * From the Broadwell PRM, volume 7, page 671:
- *
- * "Logic Ops are supported on all blendable render targets and render
- * targets with *INT formats."
- */
- if (ilo_dev_gen(dev) < ILO_GEN(8) && rt->logicop_enable)
- assert(rt->cv_is_unorm);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 361:
- *
- * "Only certain surface formats support Color Buffer Blending. Refer
- * to the Surface Format tables in Sampling Engine. Blending must be
- * disabled on a RenderTarget if blending is not supported."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 365:
- *
- * "Color Buffer Blending and Logic Ops must not be enabled
- * simultaneously, or behavior is UNDEFINED."
- */
- if (rt->blend_enable)
- assert(!rt->cv_is_integer && !rt->logicop_enable);
-
- *dst = *rt;
- if (rt->blend_enable) {
- /* 0x0 is reserved in enum gen_blend_factor */
- assert(rt->rgb_src && rt->rgb_dst && rt->a_src && rt->a_dst);
-
- if (rt->force_dst_alpha_one) {
- dst->rgb_src = get_dst_alpha_one_blend_factor(rt->rgb_src, true);
- dst->rgb_dst = get_dst_alpha_one_blend_factor(rt->rgb_dst, true);
- dst->a_src = get_dst_alpha_one_blend_factor(rt->a_src, false);
- dst->a_dst = get_dst_alpha_one_blend_factor(rt->a_dst, false);
- dst->force_dst_alpha_one = false;
- }
- } else {
- dst->rgb_src = GEN6_BLENDFACTOR_ONE;
- dst->rgb_dst = GEN6_BLENDFACTOR_ZERO;
- dst->rgb_func = GEN6_BLENDFUNCTION_ADD;
- dst->a_src = dst->rgb_src;
- dst->a_dst = dst->rgb_dst;
- dst->a_func = dst->rgb_func;
- }
-}
-
-static bool
-cc_set_gen6_BLEND_STATE(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_alpha_info *alpha = &info->alpha;
- const struct ilo_state_cc_blend_info *blend = &info->blend;
- uint32_t dw_rt[2 * ILO_STATE_CC_BLEND_MAX_RT_COUNT], dw1_invariant;
- uint32_t dw0, dw1;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 7.5);
-
- if (!cc_validate_gen6_alpha(dev, info) ||
- !cc_validate_gen6_blend(dev, info))
- return false;
-
- /*
- * According to the Sandy Bridge PRM, volume 2 part 1, page 360, pre-blend
- * and post-blend color clamps must be enabled in most cases. For the
- * other cases, they are either desirable or ignored. We can enable them
- * unconditionally.
- */
- dw1 = GEN6_RT_DW1_COLORCLAMP_RTFORMAT |
- GEN6_RT_DW1_PRE_BLEND_CLAMP |
- GEN6_RT_DW1_POST_BLEND_CLAMP;
-
- if (alpha->alpha_to_coverage) {
- dw1 |= GEN6_RT_DW1_ALPHA_TO_COVERAGE;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 379:
- *
- * "[DevSNB]: This bit (AlphaToCoverage Dither Enable) must be
- * disabled."
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- dw1 |= GEN6_RT_DW1_ALPHA_TO_COVERAGE_DITHER;
- }
-
- if (alpha->alpha_to_one)
- dw1 |= GEN6_RT_DW1_ALPHA_TO_ONE;
-
- if (alpha->test_enable) {
- dw1 |= GEN6_RT_DW1_ALPHA_TEST_ENABLE |
- alpha->test_func << GEN6_RT_DW1_ALPHA_TEST_FUNC__SHIFT;
- } else {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 371:
- *
- * "When Alpha Test is disabled, Alpha Test Function must be
- * COMPAREFUNCTION_ALWAYS."
- */
- dw1 |= GEN6_COMPAREFUNCTION_ALWAYS <<
- GEN6_RT_DW1_ALPHA_TEST_FUNC__SHIFT;
- }
-
- if (blend->dither_enable)
- dw1 |= GEN6_RT_DW1_DITHER_ENABLE;
-
- dw1_invariant = dw1;
-
- for (i = 0; i < blend->rt_count; i++) {
- struct ilo_state_cc_blend_rt_info rt;
-
- cc_get_gen6_effective_rt(dev, info, i, &rt);
-
- /* 0x0 is reserved for blend factors and we have to set them all */
- dw0 = rt.a_func << GEN6_RT_DW0_ALPHA_FUNC__SHIFT |
- rt.a_src << GEN6_RT_DW0_SRC_ALPHA_FACTOR__SHIFT |
- rt.a_dst << GEN6_RT_DW0_DST_ALPHA_FACTOR__SHIFT |
- rt.rgb_func << GEN6_RT_DW0_COLOR_FUNC__SHIFT |
- rt.rgb_src << GEN6_RT_DW0_SRC_COLOR_FACTOR__SHIFT |
- rt.rgb_dst << GEN6_RT_DW0_DST_COLOR_FACTOR__SHIFT;
-
- if (rt.blend_enable) {
- dw0 |= GEN6_RT_DW0_BLEND_ENABLE;
-
- if (rt.a_src != rt.rgb_src ||
- rt.a_dst != rt.rgb_dst ||
- rt.a_func != rt.rgb_func)
- dw0 |= GEN6_RT_DW0_INDEPENDENT_ALPHA_ENABLE;
- }
-
- dw1 = dw1_invariant |
- rt.argb_write_disables << GEN6_RT_DW1_WRITE_DISABLES__SHIFT;
-
- if (rt.logicop_enable) {
- dw1 |= GEN6_RT_DW1_LOGICOP_ENABLE |
- rt.logicop_func << GEN6_RT_DW1_LOGICOP_FUNC__SHIFT;
- }
-
- dw_rt[2 * i + 0] = dw0;
- dw_rt[2 * i + 1] = dw1;
- }
-
-
- STATIC_ASSERT(ARRAY_SIZE(cc->blend) >= ARRAY_SIZE(dw_rt));
- memcpy(&cc->blend[0], dw_rt, sizeof(uint32_t) * 2 * blend->rt_count);
- cc->blend_state_count = info->blend.rt_count;
-
- return true;
-}
-
-static bool
-cc_set_gen8_BLEND_STATE(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_alpha_info *alpha = &info->alpha;
- const struct ilo_state_cc_blend_info *blend = &info->blend;
- uint32_t dw_rt[2 * ILO_STATE_CC_BLEND_MAX_RT_COUNT], dw0, dw1;
- bool indep_alpha_enable;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- if (!cc_validate_gen6_alpha(dev, info) ||
- !cc_validate_gen6_blend(dev, info))
- return false;
-
- indep_alpha_enable = false;
- for (i = 0; i < blend->rt_count; i++) {
- struct ilo_state_cc_blend_rt_info rt;
-
- cc_get_gen6_effective_rt(dev, info, i, &rt);
-
- dw0 = rt.rgb_src << GEN8_RT_DW0_SRC_COLOR_FACTOR__SHIFT |
- rt.rgb_dst << GEN8_RT_DW0_DST_COLOR_FACTOR__SHIFT |
- rt.rgb_func << GEN8_RT_DW0_COLOR_FUNC__SHIFT |
- rt.a_src << GEN8_RT_DW0_SRC_ALPHA_FACTOR__SHIFT |
- rt.a_dst << GEN8_RT_DW0_DST_ALPHA_FACTOR__SHIFT |
- rt.a_func << GEN8_RT_DW0_ALPHA_FUNC__SHIFT |
- rt.argb_write_disables << GEN8_RT_DW0_WRITE_DISABLES__SHIFT;
-
- if (rt.blend_enable) {
- dw0 |= GEN8_RT_DW0_BLEND_ENABLE;
-
- if (rt.a_src != rt.rgb_src ||
- rt.a_dst != rt.rgb_dst ||
- rt.a_func != rt.rgb_func)
- indep_alpha_enable = true;
- }
-
- dw1 = GEN8_RT_DW1_COLORCLAMP_RTFORMAT |
- GEN8_RT_DW1_PRE_BLEND_CLAMP |
- GEN8_RT_DW1_POST_BLEND_CLAMP;
-
- if (rt.logicop_enable) {
- dw1 |= GEN8_RT_DW1_LOGICOP_ENABLE |
- rt.logicop_func << GEN8_RT_DW1_LOGICOP_FUNC__SHIFT;
- }
-
- dw_rt[2 * i + 0] = dw0;
- dw_rt[2 * i + 1] = dw1;
- }
-
- dw0 = 0;
-
- if (alpha->alpha_to_coverage) {
- dw0 |= GEN8_BLEND_DW0_ALPHA_TO_COVERAGE |
- GEN8_BLEND_DW0_ALPHA_TO_COVERAGE_DITHER;
- }
-
- if (indep_alpha_enable)
- dw0 |= GEN8_BLEND_DW0_INDEPENDENT_ALPHA_ENABLE;
-
- if (alpha->alpha_to_one)
- dw0 |= GEN8_BLEND_DW0_ALPHA_TO_ONE;
-
- if (alpha->test_enable) {
- dw0 |= GEN8_BLEND_DW0_ALPHA_TEST_ENABLE |
- alpha->test_func << GEN8_BLEND_DW0_ALPHA_TEST_FUNC__SHIFT;
- } else {
- dw0 |= GEN6_COMPAREFUNCTION_ALWAYS <<
- GEN8_BLEND_DW0_ALPHA_TEST_FUNC__SHIFT;
- }
-
- if (blend->dither_enable)
- dw0 |= GEN8_BLEND_DW0_DITHER_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(cc->blend) >= 2 + ARRAY_SIZE(dw_rt));
- cc->blend[1] = dw0;
- memcpy(&cc->blend[2], dw_rt, sizeof(uint32_t) * 2 * blend->rt_count);
- cc->blend_state_count = info->blend.rt_count;
-
- return true;
-}
-
-static bool
-cc_set_gen8_3DSTATE_PS_BLEND(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- const struct ilo_state_cc_alpha_info *alpha = &info->alpha;
- const struct ilo_state_cc_blend_info *blend = &info->blend;
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- dw1 = 0;
-
- if (alpha->alpha_to_coverage)
- dw1 |= GEN8_PS_BLEND_DW1_ALPHA_TO_COVERAGE;
-
- if (alpha->test_enable)
- dw1 |= GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE;
-
- if (blend->rt_count) {
- struct ilo_state_cc_blend_rt_info rt0;
- uint8_t i;
-
- cc_get_gen6_effective_rt(dev, info, 0, &rt0);
-
- /* 0x0 is reserved for blend factors and we have to set them all */
- dw1 |= rt0.a_src << GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__SHIFT |
- rt0.a_dst << GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__SHIFT |
- rt0.rgb_src << GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__SHIFT |
- rt0.rgb_dst << GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__SHIFT;
-
- for (i = 0; i < blend->rt_count; i++) {
- if (blend->rt[i].argb_write_disables != 0xf) {
- dw1 |= GEN8_PS_BLEND_DW1_WRITABLE_RT;
- break;
- }
- }
-
- if (rt0.blend_enable) {
- dw1 |= GEN8_PS_BLEND_DW1_RT0_BLEND_ENABLE;
-
- if (rt0.a_src != rt0.rgb_src || rt0.a_dst != rt0.rgb_dst)
- dw1 |= GEN8_PS_BLEND_DW1_RT0_INDEPENDENT_ALPHA_ENABLE;
- }
- }
-
- STATIC_ASSERT(ARRAY_SIZE(cc->blend) >= 1);
- cc->blend[0] = dw1;
-
- return true;
-}
-
-static bool
-cc_params_set_gen6_COLOR_CALC_STATE(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_params_info *params)
-{
- uint32_t dw0;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- dw0 = params->stencil_front.test_ref << GEN6_CC_DW0_STENCIL_REF__SHIFT |
- params->stencil_back.test_ref << GEN6_CC_DW0_STENCIL1_REF__SHIFT |
- GEN6_CC_DW0_ALPHATEST_FLOAT32;
-
- STATIC_ASSERT(ARRAY_SIZE(cc->cc) >= 6);
- cc->cc[0] = dw0;
- cc->cc[1] = fui(params->alpha_ref);
- cc->cc[2] = fui(params->blend_rgba[0]);
- cc->cc[3] = fui(params->blend_rgba[1]);
- cc->cc[4] = fui(params->blend_rgba[2]);
- cc->cc[5] = fui(params->blend_rgba[3]);
-
- return true;
-}
-
-bool
-ilo_state_cc_init(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- assert(ilo_is_zeroed(cc, sizeof(*cc)));
- return ilo_state_cc_set_info(cc, dev, info);
-}
-
-bool
-ilo_state_cc_set_info(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info)
-{
- bool ret = true;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- ret &= cc_set_gen8_3DSTATE_WM_DEPTH_STENCIL(cc, dev, info);
- ret &= cc_set_gen8_BLEND_STATE(cc, dev, info);
- ret &= cc_set_gen8_3DSTATE_PS_BLEND(cc, dev, info);
- } else {
- ret &= cc_set_gen6_DEPTH_STENCIL_STATE(cc, dev, info);
- ret &= cc_set_gen6_BLEND_STATE(cc, dev, info);
- }
-
- ret &= cc_params_set_gen6_COLOR_CALC_STATE(cc, dev, &info->params);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_cc_set_params(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_params_info *params)
-{
- /* modify stencil masks */
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- uint32_t dw1 = cc->ds[0];
- uint32_t dw2 = cc->ds[1];
-
- if (dw1 & GEN8_ZS_DW1_STENCIL_TEST_ENABLE) {
- const bool twosided_enable = (dw1 & GEN8_ZS_DW1_STENCIL1_ENABLE);
- const struct ilo_state_cc_stencil_params_info *front_p =
- &params->stencil_front;
- const struct ilo_state_cc_stencil_params_info *back_p =
- (twosided_enable) ? &params->stencil_back :
- &params->stencil_front;
-
- if (front_p->write_mask || back_p->write_mask)
- dw1 |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
- else
- dw1 &= ~GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
-
- dw2 =
- front_p->test_mask << GEN8_ZS_DW2_STENCIL_TEST_MASK__SHIFT |
- front_p->write_mask << GEN8_ZS_DW2_STENCIL_WRITE_MASK__SHIFT |
- back_p->test_mask << GEN8_ZS_DW2_STENCIL1_TEST_MASK__SHIFT |
- back_p->write_mask << GEN8_ZS_DW2_STENCIL1_WRITE_MASK__SHIFT;
- }
-
- cc->ds[0] = dw1;
- cc->ds[1] = dw2;
- } else {
- uint32_t dw0 = cc->ds[0];
- uint32_t dw1 = cc->ds[1];
-
- if (dw0 & GEN6_ZS_DW0_STENCIL_TEST_ENABLE) {
- const bool twosided_enable = (dw0 & GEN6_ZS_DW0_STENCIL1_ENABLE);
- const struct ilo_state_cc_stencil_params_info *front_p =
- &params->stencil_front;
- const struct ilo_state_cc_stencil_params_info *back_p =
- (twosided_enable) ? &params->stencil_back :
- &params->stencil_front;
-
- if (front_p->write_mask || back_p->write_mask)
- dw0 |= GEN6_ZS_DW0_STENCIL_WRITE_ENABLE;
- else
- dw0 &= ~GEN6_ZS_DW0_STENCIL_WRITE_ENABLE;
-
- dw1 =
- front_p->test_mask << GEN6_ZS_DW1_STENCIL_TEST_MASK__SHIFT |
- front_p->write_mask << GEN6_ZS_DW1_STENCIL_WRITE_MASK__SHIFT |
- back_p->test_mask << GEN6_ZS_DW1_STENCIL1_TEST_MASK__SHIFT |
- back_p->write_mask << GEN6_ZS_DW1_STENCIL1_WRITE_MASK__SHIFT;
- }
-
- cc->ds[0] = dw0;
- cc->ds[1] = dw1;
- }
-
- /* modify COLOR_CALC_STATE */
- cc_params_set_gen6_COLOR_CALC_STATE(cc, dev, params);
-
- return true;
-}
-
-void
-ilo_state_cc_full_delta(const struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- struct ilo_state_cc_delta *delta)
-{
- delta->dirty = ILO_STATE_CC_BLEND_STATE |
- ILO_STATE_CC_COLOR_CALC_STATE;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- delta->dirty |= ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL |
- ILO_STATE_CC_3DSTATE_PS_BLEND;
- } else {
- delta->dirty |= ILO_STATE_CC_DEPTH_STENCIL_STATE;
- }
-}
-
-void
-ilo_state_cc_get_delta(const struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc *old,
- struct ilo_state_cc_delta *delta)
-{
- delta->dirty = 0;
-
- if (memcmp(cc->ds, old->ds, sizeof(cc->ds))) {
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- delta->dirty |= ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL;
- else
- delta->dirty |= ILO_STATE_CC_DEPTH_STENCIL_STATE;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- if (cc->blend[0] != old->blend[0])
- delta->dirty |= ILO_STATE_CC_3DSTATE_PS_BLEND;
-
- if (memcmp(&cc->blend[1], &old->blend[1],
- sizeof(uint32_t) * (1 + 2 * cc->blend_state_count)))
- delta->dirty |= ILO_STATE_CC_BLEND_STATE;
- } else if (memcmp(cc->blend, old->blend,
- sizeof(uint32_t) * 2 * cc->blend_state_count)) {
- delta->dirty |= ILO_STATE_CC_BLEND_STATE;
- }
-
- if (memcmp(cc->cc, old->cc, sizeof(cc->cc)))
- delta->dirty |= ILO_STATE_CC_COLOR_CALC_STATE;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_state_cc.h b/src/gallium/drivers/ilo/core/ilo_state_cc.h
deleted file mode 100644
index 5b96a60f988..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_cc.h
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_CC_H
-#define ILO_STATE_CC_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Sandy Bridge PRM, volume 2 part 1, page 38:
- *
- * "Render Target Index. Specifies the render target index that will be
- * used to select blend state from BLEND_STATE.
- * Format = U3"
- */
-#define ILO_STATE_CC_BLEND_MAX_RT_COUNT 8
-
-enum ilo_state_cc_dirty_bits {
- ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL = (1 << 0),
- ILO_STATE_CC_3DSTATE_PS_BLEND = (1 << 1),
- ILO_STATE_CC_DEPTH_STENCIL_STATE = (1 << 2),
- ILO_STATE_CC_BLEND_STATE = (1 << 3),
- ILO_STATE_CC_COLOR_CALC_STATE = (1 << 4),
-};
-
-/**
- * AlphaCoverage and AlphaTest.
- */
-struct ilo_state_cc_alpha_info {
- bool cv_sample_count_one;
- bool cv_float_source0_alpha;
-
- bool alpha_to_coverage;
- bool alpha_to_one;
-
- bool test_enable;
- enum gen_compare_function test_func;
-};
-
-struct ilo_state_cc_stencil_op_info {
- enum gen_compare_function test_func;
- enum gen_stencil_op fail_op;
- enum gen_stencil_op zfail_op;
- enum gen_stencil_op zpass_op;
-};
-
-/**
- * StencilTest.
- */
-struct ilo_state_cc_stencil_info {
- bool cv_has_buffer;
-
- bool test_enable;
- bool twosided_enable;
-
- struct ilo_state_cc_stencil_op_info front;
- struct ilo_state_cc_stencil_op_info back;
-};
-
-/**
- * DepthTest.
- */
-struct ilo_state_cc_depth_info {
- bool cv_has_buffer;
-
- bool test_enable;
- /* independent from test_enable */
- bool write_enable;
-
- enum gen_compare_function test_func;
-};
-
-struct ilo_state_cc_blend_rt_info {
- bool cv_has_buffer;
- bool cv_is_unorm;
- bool cv_is_integer;
-
- uint8_t argb_write_disables;
-
- bool logicop_enable;
- enum gen_logic_op logicop_func;
-
- bool blend_enable;
- bool force_dst_alpha_one;
- enum gen_blend_factor rgb_src;
- enum gen_blend_factor rgb_dst;
- enum gen_blend_function rgb_func;
- enum gen_blend_factor a_src;
- enum gen_blend_factor a_dst;
- enum gen_blend_function a_func;
-};
-
-/**
- * ColorBufferBlending, Dithering, and LogicOps.
- */
-struct ilo_state_cc_blend_info {
- const struct ilo_state_cc_blend_rt_info *rt;
- uint8_t rt_count;
-
- bool dither_enable;
-};
-
-struct ilo_state_cc_stencil_params_info {
- uint8_t test_ref;
- uint8_t test_mask;
- uint8_t write_mask;
-};
-
-/**
- * CC parameters.
- */
-struct ilo_state_cc_params_info {
- float alpha_ref;
-
- struct ilo_state_cc_stencil_params_info stencil_front;
- struct ilo_state_cc_stencil_params_info stencil_back;
-
- float blend_rgba[4];
-};
-
-/**
- * Pixel processing.
- */
-struct ilo_state_cc_info {
- struct ilo_state_cc_alpha_info alpha;
- struct ilo_state_cc_stencil_info stencil;
- struct ilo_state_cc_depth_info depth;
- struct ilo_state_cc_blend_info blend;
-
- struct ilo_state_cc_params_info params;
-};
-
-struct ilo_state_cc {
- uint32_t ds[3];
-
- uint8_t blend_state_count;
- uint32_t blend[1 + 1 + 2 * ILO_STATE_CC_BLEND_MAX_RT_COUNT];
-
- uint32_t cc[6];
-};
-
-struct ilo_state_cc_delta {
- uint32_t dirty;
-};
-
-bool
-ilo_state_cc_init(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info);
-
-bool
-ilo_state_cc_set_info(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_info *info);
-
-bool
-ilo_state_cc_set_params(struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc_params_info *params);
-
-void
-ilo_state_cc_full_delta(const struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- struct ilo_state_cc_delta *delta);
-
-void
-ilo_state_cc_get_delta(const struct ilo_state_cc *cc,
- const struct ilo_dev *dev,
- const struct ilo_state_cc *old,
- struct ilo_state_cc_delta *delta);
-
-#endif /* ILO_STATE_CC_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_state_compute.c b/src/gallium/drivers/ilo/core/ilo_state_compute.c
deleted file mode 100644
index ba3ff9001e1..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_compute.c
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_compute.h"
-
-struct compute_urb_configuration {
- int idrt_entry_count;
- int curbe_entry_count;
-
- int urb_entry_count;
- /* in 256-bit register increments */
- int urb_entry_size;
-};
-
-static int
-get_gen6_rob_entry_count(const struct ilo_dev *dev)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 60:
- *
- * "ROB has 64KB of storage; 2048 entries."
- *
- * From the valid ranges of "CURBE Allocation Size", we can also conclude
- * that interface entries and CURBE data must be in ROB. And that ROB
- * should be 16KB, or 512 entries, on Gen7 GT1.
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- return 2048;
- else if (ilo_dev_gen(dev) >= ILO_GEN(7))
- return (dev->gt == 2) ? 2048 : 512;
- else
- return (dev->gt == 2) ? 2048 : 1024;
-}
-
-static int
-get_gen6_idrt_entry_count(const struct ilo_dev *dev)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 21:
- *
- * "The first 32 URB entries are reserved for the interface
- * descriptor..."
- *
- * From the Haswell PRM, volume 7, page 836:
- *
- * "The first 64 URB entries are reserved for the interface
- * description..."
- */
- return (ilo_dev_gen(dev) >= ILO_GEN(7.5)) ? 64 : 32;
-}
-
-static int
-get_gen6_curbe_entry_count(const struct ilo_dev *dev, uint32_t curbe_size)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 21:
- *
- * "(CURBE Allocation Size) Specifies the total length allocated for
- * CURBE, in 256-bit register increments.
- */
- const int entry_count = (curbe_size + 31) / 32;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(get_gen6_idrt_entry_count(dev) + entry_count <=
- get_gen6_rob_entry_count(dev));
-
- return entry_count;
-}
-
-static bool
-compute_get_gen6_urb_configuration(const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info,
- struct compute_urb_configuration *urb)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- urb->idrt_entry_count = get_gen6_idrt_entry_count(dev);
- urb->curbe_entry_count =
- get_gen6_curbe_entry_count(dev, info->curbe_alloc_size);
-
- /*
- * From the Broadwell PRM, volume 2b, page 451:
- *
- * "Please note that 0 is not allowed for this field (Number of URB
- * Entries)."
- */
- urb->urb_entry_count = (ilo_dev_gen(dev) >= ILO_GEN(8)) ? 1 : 0;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 52:
- *
- * "(URB Entry Allocation Size) Specifies the length of each URB entry
- * used by the unit, in 256-bit register increments - 1."
- */
- urb->urb_entry_size = 1;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 22:
- *
- * MEDIA_VFE_STATE specifies the amount of CURBE space, the URB handle
- * size and the number of URB handles. The driver must ensure that
- * ((URB_handle_size * URB_num_handle) - CURBE - 32) <=
- * URB_allocation_in_L3."
- */
- assert(urb->idrt_entry_count + urb->curbe_entry_count +
- urb->urb_entry_count * urb->urb_entry_size <=
- info->cv_urb_alloc_size / 32);
-
- return true;
-}
-
-static int
-compute_interface_get_gen6_read_end(const struct ilo_dev *dev,
- const struct ilo_state_compute_interface_info *interface)
-{
- const int per_thread_read = (interface->curbe_read_length + 31) / 32;
- const int cross_thread_read =
- (interface->cross_thread_curbe_read_length + 31) / 32;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(interface->curbe_read_offset % 32 == 0);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 60:
- *
- * "(Constant URB Entry Read Length) [0,63]"
- */
- assert(per_thread_read <= 63);
-
- /*
- * From the Haswell PRM, volume 2d, page 199:
- *
- * "(Cross-Thread Constant Data Read Length) [0,127]"
- */
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- assert(cross_thread_read <= 127);
- else
- assert(!cross_thread_read);
-
- if (per_thread_read || cross_thread_read) {
- return interface->curbe_read_offset / 32 + cross_thread_read +
- per_thread_read * interface->thread_group_size;
- } else {
- return 0;
- }
-}
-
-static bool
-compute_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info,
- const struct compute_urb_configuration *urb)
-{
- int min_curbe_entry_count;
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(info->interface_count <= urb->idrt_entry_count);
-
- min_curbe_entry_count = 0;
- for (i = 0; i < info->interface_count; i++) {
- const int read_end =
- compute_interface_get_gen6_read_end(dev, &info->interfaces[i]);
-
- if (min_curbe_entry_count < read_end)
- min_curbe_entry_count = read_end;
- }
-
- assert(min_curbe_entry_count <= urb->curbe_entry_count);
-
- /*
- * From the Broadwell PRM, volume 2b, page 452:
- *
- * "CURBE Allocation Size should be 0 for GPGPU workloads that uses
- * indirect instead of CURBE."
- */
- if (!min_curbe_entry_count)
- assert(!urb->curbe_entry_count);
-
- return true;
-}
-
-static uint32_t
-compute_get_gen6_per_thread_scratch_size(const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info,
- uint8_t *per_thread_space)
-{
- ILO_DEV_ASSERT(dev, 6, 7);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 2, page 30:
- *
- * "(Per Thread Scratch Space)
- * Range = [0,11] indicating [1k bytes, 12k bytes] [DevSNB]"
- */
- assert(info->per_thread_scratch_size <= 12 * 1024);
-
- if (!info->per_thread_scratch_size) {
- *per_thread_space = 0;
- return 0;
- }
-
- *per_thread_space = (info->per_thread_scratch_size > 1024) ?
- (info->per_thread_scratch_size - 1) / 1024 : 0;
-
- return 1024 * (1 + *per_thread_space);
-}
-
-static uint32_t
-compute_get_gen75_per_thread_scratch_size(const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info,
- uint8_t *per_thread_space)
-{
- ILO_DEV_ASSERT(dev, 7.5, 8);
-
- /*
- * From the Haswell PRM, volume 2b, page 407:
- *
- * "(Per Thread Scratch Space)
- * [0,10] Indicating [2k bytes, 2 Mbytes]"
- *
- * "Note: The scratch space should be declared as 2x the desired
- * scratch space. The stack will start at the half-way point instead
- * of the end. The upper half of scratch space will not be accessed
- * and so does not have to be allocated in memory."
- *
- * From the Broadwell PRM, volume 2a, page 450:
- *
- * "(Per Thread Scratch Space)
- * [0,11] indicating [1k bytes, 2 Mbytes]"
- */
- assert(info->per_thread_scratch_size <=
- ((ilo_dev_gen(dev) >= ILO_GEN(8)) ? 2 : 1) * 1024 * 1024);
-
- if (!info->per_thread_scratch_size) {
- *per_thread_space = 0;
- return 0;
- }
-
- /* next power of two, starting from 1KB */
- *per_thread_space = (info->per_thread_scratch_size > 1024) ?
- (util_last_bit(info->per_thread_scratch_size - 1) - 10) : 0;
-
- return 1 << (10 + *per_thread_space);
-}
-
-static bool
-compute_set_gen6_MEDIA_VFE_STATE(struct ilo_state_compute *compute,
- const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info)
-{
- struct compute_urb_configuration urb;
- uint32_t per_thread_size;
- uint8_t per_thread_space;
-
- uint32_t dw1, dw2, dw4;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!compute_get_gen6_urb_configuration(dev, info, &urb) ||
- !compute_validate_gen6(dev, info, &urb))
- return false;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- per_thread_size = compute_get_gen75_per_thread_scratch_size(dev,
- info, &per_thread_space);
- } else {
- per_thread_size = compute_get_gen6_per_thread_scratch_size(dev,
- info, &per_thread_space);
- }
-
- dw1 = per_thread_space << GEN6_VFE_DW1_SCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw2 = (dev->thread_count - 1) << GEN6_VFE_DW2_MAX_THREADS__SHIFT |
- urb.urb_entry_count << GEN6_VFE_DW2_URB_ENTRY_COUNT__SHIFT |
- GEN6_VFE_DW2_RESET_GATEWAY_TIMER |
- GEN6_VFE_DW2_BYPASS_GATEWAY_CONTROL;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && ilo_dev_gen(dev) <= ILO_GEN(7.5))
- dw2 |= GEN7_VFE_DW2_GPGPU_MODE;
-
- assert(urb.urb_entry_size);
-
- dw4 = (urb.urb_entry_size - 1) << GEN6_VFE_DW4_URB_ENTRY_SIZE__SHIFT |
- urb.curbe_entry_count << GEN6_VFE_DW4_CURBE_SIZE__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(compute->vfe) >= 3);
- compute->vfe[0] = dw1;
- compute->vfe[1] = dw2;
- compute->vfe[2] = dw4;
-
- compute->scratch_size = per_thread_size * dev->thread_count;
-
- return true;
-}
-
-static uint8_t
-compute_interface_get_gen6_sampler_count(const struct ilo_dev *dev,
- const struct ilo_state_compute_interface_info *interface)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
- return (interface->sampler_count <= 12) ?
- (interface->sampler_count + 3) / 4 : 4;
-}
-
-static uint8_t
-compute_interface_get_gen6_surface_count(const struct ilo_dev *dev,
- const struct ilo_state_compute_interface_info *interface)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
- return (interface->surface_count <= 31) ? interface->surface_count : 31;
-}
-
-static uint8_t
-compute_interface_get_gen7_slm_size(const struct ilo_dev *dev,
- const struct ilo_state_compute_interface_info *interface)
-{
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 2, page 61:
- *
- * "The amount is specified in 4k blocks, but only powers of 2 are
- * allowed: 0, 4k, 8k, 16k, 32k and 64k per half-slice."
- */
- assert(interface->slm_size <= 64 * 1024);
-
- return util_next_power_of_two((interface->slm_size + 4095) / 4096);
-}
-
-static bool
-compute_set_gen6_INTERFACE_DESCRIPTOR_DATA(struct ilo_state_compute *compute,
- const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info)
-{
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- for (i = 0; i < info->interface_count; i++) {
- const struct ilo_state_compute_interface_info *interface =
- &info->interfaces[i];
- uint16_t read_offset, per_thread_read_len, cross_thread_read_len;
- uint8_t sampler_count, surface_count;
- uint32_t dw0, dw2, dw3, dw4, dw5, dw6;
-
- assert(interface->kernel_offset % 64 == 0);
- assert(interface->thread_group_size);
-
- read_offset = interface->curbe_read_offset / 32;
- per_thread_read_len = (interface->curbe_read_length + 31) / 32;
- cross_thread_read_len =
- (interface->cross_thread_curbe_read_length + 31) / 32;
-
- sampler_count =
- compute_interface_get_gen6_sampler_count(dev, interface);
- surface_count =
- compute_interface_get_gen6_surface_count(dev, interface);
-
- dw0 = interface->kernel_offset;
- dw2 = sampler_count << GEN6_IDRT_DW2_SAMPLER_COUNT__SHIFT;
- dw3 = surface_count << GEN6_IDRT_DW3_BINDING_TABLE_SIZE__SHIFT;
- dw4 = per_thread_read_len << GEN6_IDRT_DW4_CURBE_READ_LEN__SHIFT |
- read_offset << GEN6_IDRT_DW4_CURBE_READ_OFFSET__SHIFT;
-
- dw5 = 0;
- dw6 = 0;
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- const uint8_t slm_size =
- compute_interface_get_gen7_slm_size(dev, interface);
-
- dw5 |= GEN7_IDRT_DW5_ROUNDING_MODE_RTNE;
-
- if (slm_size) {
- dw5 |= GEN7_IDRT_DW5_BARRIER_ENABLE |
- slm_size << GEN7_IDRT_DW5_SLM_SIZE__SHIFT;
- }
-
- /*
- * From the Haswell PRM, volume 2d, page 199:
- *
- * "(Number of Threads in GPGPU Thread Group) Specifies the
- * number of threads that are in this thread group. Used to
- * program the barrier for the number of messages to expect. The
- * minimum value is 0 (which will disable the barrier), while
- * the maximum value is the number of threads in a subslice for
- * local barriers."
- *
- * From the Broadwell PRM, volume 2d, page 183:
- *
- * "(Number of Threads in GPGPU Thread Group) Specifies the
- * number of threads that are in this thread group. The minimum
- * value is 1, while the maximum value is the number of threads
- * in a subslice for local barriers. See vol1b Configurations
- * for the number of threads per subslice for different
- * products. The maximum value for global barriers is limited
- * by the number of threads in the system, or by 511, whichever
- * is lower. This field should not be set to 0 even if the
- * barrier is disabled, since an accurate value is needed for
- * proper pre-emption."
- */
- if (slm_size || ilo_dev_gen(dev) >= ILO_GEN(8)) {
- dw5 |= interface->thread_group_size <<
- GEN7_IDRT_DW5_THREAD_GROUP_SIZE__SHIFT;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- dw6 |= cross_thread_read_len <<
- GEN75_IDRT_DW6_CROSS_THREAD_CURBE_READ_LEN__SHIFT;
- }
- }
-
- STATIC_ASSERT(ARRAY_SIZE(compute->idrt[i]) >= 6);
- compute->idrt[i][0] = dw0;
- compute->idrt[i][1] = dw2;
- compute->idrt[i][2] = dw3;
- compute->idrt[i][3] = dw4;
- compute->idrt[i][4] = dw5;
- compute->idrt[i][5] = dw6;
- }
-
- return true;
-}
-
-bool
-ilo_state_compute_init(struct ilo_state_compute *compute,
- const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(compute, sizeof(*compute)));
- assert(ilo_is_zeroed(info->data, info->data_size));
-
- assert(ilo_state_compute_data_size(dev, info->interface_count) <=
- info->data_size);
- compute->idrt = (uint32_t (*)[6]) info->data;
-
- ret &= compute_set_gen6_MEDIA_VFE_STATE(compute, dev, info);
- ret &= compute_set_gen6_INTERFACE_DESCRIPTOR_DATA(compute, dev, info);
-
- assert(ret);
-
- return ret;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_state_compute.h b/src/gallium/drivers/ilo/core/ilo_state_compute.h
deleted file mode 100644
index bd56bba4369..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_compute.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_COMPUTE_H
-#define ILO_STATE_COMPUTE_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Haswell PRM, volume 7, page 836:
- *
- * "The first 64 URB entries are reserved for the interface
- * description..."
- */
-#define ILO_STATE_COMPUTE_MAX_INTERFACE_COUNT 64
-
-struct ilo_state_compute_interface_info {
- /* usually 0 unless there are multiple interfaces */
- uint32_t kernel_offset;
-
- uint8_t sampler_count;
- uint8_t surface_count;
-
- uint16_t thread_group_size;
- uint32_t slm_size;
-
- uint16_t curbe_read_offset;
- uint16_t curbe_read_length;
- uint16_t cross_thread_curbe_read_length;
-};
-
-struct ilo_state_compute_info {
- void *data;
- size_t data_size;
-
- const struct ilo_state_compute_interface_info *interfaces;
- uint8_t interface_count;
-
- uint32_t per_thread_scratch_size;
-
- uint32_t cv_urb_alloc_size;
- uint32_t curbe_alloc_size;
-};
-
-struct ilo_state_compute {
- uint32_t vfe[3];
-
- uint32_t (*idrt)[6];
- uint8_t idrt_count;
-
- uint32_t scratch_size;
-};
-
-static inline size_t
-ilo_state_compute_data_size(const struct ilo_dev *dev,
- uint8_t interface_count)
-{
- const struct ilo_state_compute *compute = NULL;
- return sizeof(compute->idrt[0]) * interface_count;
-}
-
-bool
-ilo_state_compute_init(struct ilo_state_compute *compute,
- const struct ilo_dev *dev,
- const struct ilo_state_compute_info *info);
-
-static inline uint32_t
-ilo_state_compute_get_scratch_size(const struct ilo_state_compute *compute)
-{
- return compute->scratch_size;
-}
-
-#endif /* ILO_STATE_COMPUTE_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_state_raster.c b/src/gallium/drivers/ilo/core/ilo_state_raster.c
deleted file mode 100644
index a694f71bbbf..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_raster.c
+++ /dev/null
@@ -1,1248 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_raster.h"
-
-static bool
-raster_validate_gen6_clip(const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_clip_info *clip = &info->clip;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(clip->viewport_count);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 188:
- *
- * ""Clip Distance Cull Test Enable Bitmask" and "Clip Distance Clip
- * Test Enable Bitmask" should not have overlapping bits in the mask,
- * else the results are undefined."
- */
- assert(!(clip->user_cull_enables & clip->user_clip_enables));
-
- if (ilo_dev_gen(dev) < ILO_GEN(9))
- assert(clip->z_near_enable == clip->z_far_enable);
-
- return true;
-}
-
-static bool
-raster_set_gen6_3DSTATE_CLIP(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_clip_info *clip = &info->clip;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_tri_info *tri = &info->tri;
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- uint32_t dw1, dw2, dw3;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!raster_validate_gen6_clip(dev, info))
- return false;
-
- dw1 = clip->user_cull_enables << GEN6_CLIP_DW1_UCP_CULL_ENABLES__SHIFT;
-
- if (clip->stats_enable)
- dw1 |= GEN6_CLIP_DW1_STATISTICS;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 219:
- *
- * "Workaround : Due to Hardware issue "EarlyCull" needs to be
- * enabled only for the cases where the incoming primitive topology
- * into the clipper guaranteed to be Trilist."
- *
- * What does this mean?
- */
- dw1 |= GEN7_CLIP_DW1_SUBPIXEL_8BITS |
- GEN7_CLIP_DW1_EARLY_CULL_ENABLE;
-
- if (ilo_dev_gen(dev) <= ILO_GEN(7.5)) {
- dw1 |= tri->front_winding << GEN7_CLIP_DW1_FRONT_WINDING__SHIFT |
- tri->cull_mode << GEN7_CLIP_DW1_CULL_MODE__SHIFT;
- }
- }
-
- dw2 = clip->user_clip_enables << GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT |
- GEN6_CLIPMODE_NORMAL << GEN6_CLIP_DW2_CLIP_MODE__SHIFT;
-
- if (clip->clip_enable)
- dw2 |= GEN6_CLIP_DW2_CLIP_ENABLE;
-
- if (clip->z_near_zero)
- dw2 |= GEN6_CLIP_DW2_APIMODE_D3D;
- else
- dw2 |= GEN6_CLIP_DW2_APIMODE_OGL;
-
- if (clip->xy_test_enable)
- dw2 |= GEN6_CLIP_DW2_XY_TEST_ENABLE;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8) && clip->z_near_enable)
- dw2 |= GEN6_CLIP_DW2_Z_TEST_ENABLE;
-
- if (clip->gb_test_enable)
- dw2 |= GEN6_CLIP_DW2_GB_TEST_ENABLE;
-
- if (scan->barycentric_interps & (GEN6_INTERP_NONPERSPECTIVE_PIXEL |
- GEN6_INTERP_NONPERSPECTIVE_CENTROID |
- GEN6_INTERP_NONPERSPECTIVE_SAMPLE))
- dw2 |= GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE;
-
- if (setup->first_vertex_provoking) {
- dw2 |= 0 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT |
- 0 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT |
- 1 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT;
- } else {
- dw2 |= 2 << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT |
- 1 << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT |
- 2 << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT;
- }
-
- dw3 = 0x1 << GEN6_CLIP_DW3_MIN_POINT_WIDTH__SHIFT |
- 0x7ff << GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT |
- (clip->viewport_count - 1) << GEN6_CLIP_DW3_MAX_VPINDEX__SHIFT;
-
- if (clip->force_rtaindex_zero)
- dw3 |= GEN6_CLIP_DW3_FORCE_RTAINDEX_ZERO;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->clip) >= 3);
- rs->clip[0] = dw1;
- rs->clip[1] = dw2;
- rs->clip[2] = dw3;
-
- return true;
-}
-
-static bool
-raster_params_is_gen6_line_aa_allowed(const struct ilo_dev *dev,
- const struct ilo_state_raster_params_info *params)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 251:
- *
- * "This field (Anti-aliasing Enable) must be disabled if any of the
- * render targets have integer (UINT or SINT) surface format."
- */
- if (params->any_integer_rt)
- return false;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 321:
- *
- * "[DevSNB+]: This field (Hierarchical Depth Buffer Enable) must be
- * disabled if Anti-aliasing Enable in 3DSTATE_SF is enabled.
- */
- if (ilo_dev_gen(dev) == ILO_GEN(6) && params->hiz_enable)
- return false;
-
- return true;
-}
-
-static void
-raster_get_gen6_effective_line(const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_params_info *params = &info->params;
-
- *line = info->line;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 251:
- *
- * "This field (Anti-aliasing Enable) is ignored when Multisample
- * Rasterization Mode is MSRASTMODE_ON_xx."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 251:
- *
- * "Setting a Line Width of 0.0 specifies the rasterization of the
- * "thinnest" (one-pixel-wide), non-antialiased lines. Note that
- * this effectively overrides the effect of AAEnable (though the
- * AAEnable state variable is not modified). Lines rendered with
- * zero Line Width are rasterized using GIQ (Grid Intersection
- * Quantization) rules as specified by the GDI and Direct3D APIs."
- *
- * "Software must not program a value of 0.0 when running in
- * MSRASTMODE_ON_xxx modes - zero-width lines are not available
- * when multisampling rasterization is enabled."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 294:
- *
- * "Line stipple, controlled via the Line Stipple Enable state variable
- * in WM_STATE, discards certain pixels that are produced by non-AA
- * line rasterization."
- */
- if (setup->line_msaa_enable ||
- !raster_params_is_gen6_line_aa_allowed(dev, params))
- line->aa_enable = false;
- if (setup->line_msaa_enable || line->aa_enable) {
- line->stipple_enable = false;
- line->giq_enable = false;
- line->giq_last_pixel = false;
- }
-}
-
-static bool
-raster_validate_gen8_raster(const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_tri_info *tri = &info->tri;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 249:
- *
- * "This setting (SOLID) is required when rendering rectangle
- * (RECTLIST) objects.
- */
- if (tri->fill_mode_front != GEN6_FILLMODE_SOLID ||
- tri->fill_mode_back != GEN6_FILLMODE_SOLID)
- assert(!setup->cv_is_rectangle);
-
- return true;
-}
-
-static enum gen_msrast_mode
-raster_setup_get_gen6_msrast_mode(const struct ilo_dev *dev,
- const struct ilo_state_raster_setup_info *setup)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (setup->line_msaa_enable) {
- return (setup->msaa_enable) ? GEN6_MSRASTMODE_ON_PATTERN :
- GEN6_MSRASTMODE_ON_PIXEL;
- } else {
- return (setup->msaa_enable) ? GEN6_MSRASTMODE_OFF_PATTERN :
- GEN6_MSRASTMODE_OFF_PIXEL;
- }
-}
-
-static int
-get_gen6_line_width(const struct ilo_dev *dev, float fwidth,
- bool line_aa_enable, bool line_giq_enable)
-{
- int line_width;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* in U3.7 */
- line_width = (int) (fwidth * 128.0f + 0.5f);
-
- /*
- * Smooth lines should intersect ceil(line_width) or (ceil(line_width) + 1)
- * pixels in the minor direction. We have to make the lines slightly
- * thicker, 0.5 pixel on both sides, so that they intersect that many
- * pixels.
- */
- if (line_aa_enable)
- line_width += 128;
-
- line_width = CLAMP(line_width, 1, 1023);
-
- if (line_giq_enable && line_width == 128)
- line_width = 0;
-
- return line_width;
-}
-
-static int
-get_gen6_point_width(const struct ilo_dev *dev, float fwidth)
-{
- int point_width;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* in U8.3 */
- point_width = (int) (fwidth * 8.0f + 0.5f);
- point_width = CLAMP(point_width, 1, 2047);
-
- return point_width;
-}
-
-static bool
-raster_set_gen7_3DSTATE_SF(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- const struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_clip_info *clip = &info->clip;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_point_info *point = &info->point;
- const struct ilo_state_raster_tri_info *tri = &info->tri;
- const struct ilo_state_raster_params_info *params = &info->params;
- const enum gen_msrast_mode msrast =
- raster_setup_get_gen6_msrast_mode(dev, setup);
- const int line_width = get_gen6_line_width(dev, params->line_width,
- line->aa_enable, line->giq_enable);
- const int point_width = get_gen6_point_width(dev, params->point_width);
- uint32_t dw1, dw2, dw3;
-
- ILO_DEV_ASSERT(dev, 6, 7.5);
-
- if (!raster_validate_gen8_raster(dev, info))
- return false;
-
- dw1 = tri->fill_mode_front << GEN7_SF_DW1_FILL_MODE_FRONT__SHIFT |
- tri->fill_mode_back << GEN7_SF_DW1_FILL_MODE_BACK__SHIFT |
- tri->front_winding << GEN7_SF_DW1_FRONT_WINDING__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && ilo_dev_gen(dev) <= ILO_GEN(7.5)) {
- enum gen_depth_format format;
-
- /* do it here as we want 0x0 to be valid */
- switch (tri->depth_offset_format) {
- case GEN6_ZFORMAT_D32_FLOAT_S8X24_UINT:
- format = GEN6_ZFORMAT_D32_FLOAT;
- break;
- case GEN6_ZFORMAT_D24_UNORM_S8_UINT:
- format = GEN6_ZFORMAT_D24_UNORM_X8_UINT;
- break;
- default:
- format = tri->depth_offset_format;
- break;
- }
-
- dw1 |= format << GEN7_SF_DW1_DEPTH_FORMAT__SHIFT;
- }
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 248:
- *
- * "This bit (Statistics Enable) should be set whenever clipping is
- * enabled and the Statistics Enable bit is set in CLIP_STATE. It
- * should be cleared if clipping is disabled or Statistics Enable in
- * CLIP_STATE is clear."
- */
- if (clip->stats_enable && clip->clip_enable)
- dw1 |= GEN7_SF_DW1_STATISTICS;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 258:
- *
- * "This bit (Legacy Global Depth Bias Enable, Global Depth Offset
- * Enable Solid , Global Depth Offset Enable Wireframe, and Global
- * Depth Offset Enable Point) should be set whenever non zero depth
- * bias (Slope, Bias) values are used. Setting this bit may have some
- * degradation of performance for some workloads."
- *
- * But it seems fine to ignore that.
- */
- if (tri->depth_offset_solid)
- dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_SOLID;
- if (tri->depth_offset_wireframe)
- dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME;
- if (tri->depth_offset_point)
- dw1 |= GEN7_SF_DW1_DEPTH_OFFSET_POINT;
-
- if (setup->viewport_transform)
- dw1 |= GEN7_SF_DW1_VIEWPORT_TRANSFORM;
-
- dw2 = tri->cull_mode << GEN7_SF_DW2_CULL_MODE__SHIFT |
- line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT |
- GEN7_SF_DW2_AA_LINE_CAP_1_0 |
- msrast << GEN7_SF_DW2_MSRASTMODE__SHIFT;
-
- if (line->aa_enable)
- dw2 |= GEN7_SF_DW2_AA_LINE_ENABLE;
-
- if (ilo_dev_gen(dev) == ILO_GEN(7.5) && line->stipple_enable)
- dw2 |= GEN75_SF_DW2_LINE_STIPPLE_ENABLE;
-
- if (setup->scissor_enable)
- dw2 |= GEN7_SF_DW2_SCISSOR_ENABLE;
-
- dw3 = GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE |
- GEN7_SF_DW3_SUBPIXEL_8BITS;
-
- /* this has no effect when line_width != 0 */
- if (line->giq_last_pixel)
- dw3 |= GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE;
-
- if (setup->first_vertex_provoking) {
- dw3 |= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
- 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
- 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
- } else {
- dw3 |= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
- 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
- 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
- }
-
- /* setup->point_aa_enable is ignored */
- if (!point->programmable_width) {
- dw3 |= GEN7_SF_DW3_USE_POINT_WIDTH |
- point_width << GEN7_SF_DW3_POINT_WIDTH__SHIFT;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(rs->sf) >= 3);
- rs->sf[0] = dw1;
- rs->sf[1] = dw2;
- rs->sf[2] = dw3;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->raster) >= 4);
- rs->raster[0] = 0;
- rs->raster[1] = fui(params->depth_offset_const);
- rs->raster[2] = fui(params->depth_offset_scale);
- rs->raster[3] = fui(params->depth_offset_clamp);
-
- rs->line_aa_enable = line->aa_enable;
- rs->line_giq_enable = line->giq_enable;
-
- return true;
-}
-
-static bool
-raster_set_gen8_3DSTATE_SF(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- const struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_clip_info *clip = &info->clip;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_point_info *point = &info->point;
- const struct ilo_state_raster_params_info *params = &info->params;
- const int line_width = get_gen6_line_width(dev, params->line_width,
- line->aa_enable, line->giq_enable);
- const int point_width = get_gen6_point_width(dev, params->point_width);
- uint32_t dw1, dw2, dw3;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- dw1 = 0;
-
- if (clip->stats_enable && clip->clip_enable)
- dw1 |= GEN7_SF_DW1_STATISTICS;
-
- if (setup->viewport_transform)
- dw1 |= GEN7_SF_DW1_VIEWPORT_TRANSFORM;
-
- dw2 = line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT |
- GEN7_SF_DW2_AA_LINE_CAP_1_0;
-
- dw3 = GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE |
- GEN7_SF_DW3_SUBPIXEL_8BITS;
-
- /* this has no effect when line_width != 0 */
- if (line->giq_last_pixel)
- dw3 |= GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE;
-
- if (setup->first_vertex_provoking) {
- dw3 |= 0 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
- 0 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
- 1 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
- } else {
- dw3 |= 2 << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
- 1 << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
- 2 << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT;
- }
-
- if (!point->programmable_width) {
- dw3 |= GEN7_SF_DW3_USE_POINT_WIDTH |
- point_width << GEN7_SF_DW3_POINT_WIDTH__SHIFT;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(rs->sf) >= 3);
- rs->sf[0] = dw1;
- rs->sf[1] = dw2;
- rs->sf[2] = dw3;
-
- return true;
-}
-
-static bool
-raster_set_gen8_3DSTATE_RASTER(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- const struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_clip_info *clip = &info->clip;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_point_info *point = &info->point;
- const struct ilo_state_raster_tri_info *tri = &info->tri;
- const struct ilo_state_raster_params_info *params = &info->params;
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- if (!raster_validate_gen8_raster(dev, info))
- return false;
-
- dw1 = tri->front_winding << GEN8_RASTER_DW1_FRONT_WINDING__SHIFT |
- tri->cull_mode << GEN8_RASTER_DW1_CULL_MODE__SHIFT |
- tri->fill_mode_front << GEN8_RASTER_DW1_FILL_MODE_FRONT__SHIFT |
- tri->fill_mode_back << GEN8_RASTER_DW1_FILL_MODE_BACK__SHIFT;
-
- if (point->aa_enable)
- dw1 |= GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE;
-
- /* where should line_msaa_enable be set? */
- if (setup->msaa_enable)
- dw1 |= GEN8_RASTER_DW1_DX_MULTISAMPLE_ENABLE;
-
- if (tri->depth_offset_solid)
- dw1 |= GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID;
- if (tri->depth_offset_wireframe)
- dw1 |= GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME;
- if (tri->depth_offset_point)
- dw1 |= GEN8_RASTER_DW1_DEPTH_OFFSET_POINT;
-
- if (line->aa_enable)
- dw1 |= GEN8_RASTER_DW1_AA_LINE_ENABLE;
-
- if (setup->scissor_enable)
- dw1 |= GEN8_RASTER_DW1_SCISSOR_ENABLE;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(9)) {
- if (clip->z_far_enable)
- dw1 |= GEN9_RASTER_DW1_Z_TEST_FAR_ENABLE;
- if (clip->z_near_enable)
- dw1 |= GEN9_RASTER_DW1_Z_TEST_NEAR_ENABLE;
- } else {
- if (clip->z_near_enable)
- dw1 |= GEN8_RASTER_DW1_Z_TEST_ENABLE;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(rs->raster) >= 4);
- rs->raster[0] = dw1;
- rs->raster[1] = fui(params->depth_offset_const);
- rs->raster[2] = fui(params->depth_offset_scale);
- rs->raster[3] = fui(params->depth_offset_clamp);
-
- rs->line_aa_enable = line->aa_enable;
- rs->line_giq_enable = line->giq_enable;
-
- return true;
-}
-
-static enum gen_sample_count
-get_gen6_sample_count(const struct ilo_dev *dev, uint8_t sample_count)
-{
- enum gen_sample_count c;
- int min_gen;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (sample_count) {
- case 1:
- c = GEN6_NUMSAMPLES_1;
- min_gen = ILO_GEN(6);
- break;
- case 2:
- c = GEN8_NUMSAMPLES_2;
- min_gen = ILO_GEN(8);
- break;
- case 4:
- c = GEN6_NUMSAMPLES_4;
- min_gen = ILO_GEN(6);
- break;
- case 8:
- c = GEN7_NUMSAMPLES_8;
- min_gen = ILO_GEN(7);
- break;
- default:
- assert(!"unexpected sample count");
- c = GEN6_NUMSAMPLES_1;
- break;
- }
-
- assert(ilo_dev_gen(dev) >= min_gen);
-
- return c;
-}
-
-static bool
-raster_set_gen8_3DSTATE_MULTISAMPLE(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- const enum gen_sample_count count =
- get_gen6_sample_count(dev, scan->sample_count);
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 307:
- *
- * "Setting Multisample Rasterization Mode to MSRASTMODE_xxx_PATTERN
- * when Number of Multisamples == NUMSAMPLES_1 is UNDEFINED."
- */
- if (setup->msaa_enable)
- assert(scan->sample_count > 1);
-
- dw1 = scan->pixloc << GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__SHIFT |
- count << GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->sample) >= 1);
- rs->sample[0] = dw1;
-
- return true;
-}
-
-static bool
-raster_set_gen6_3DSTATE_SAMPLE_MASK(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 294:
- *
- * "If Number of Multisamples is NUMSAMPLES_1, bits 7:1 of this field
- * (Sample Mask) must be zero.
- *
- * If Number of Multisamples is NUMSAMPLES_4, bits 7:4 of this field
- * must be zero."
- */
- const uint32_t mask = (1 << scan->sample_count) - 1;
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- dw1 = (scan->sample_mask & mask) << GEN6_SAMPLE_MASK_DW1_VAL__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->sample) >= 2);
- rs->sample[1] = dw1;
-
- return true;
-}
-
-static bool
-raster_validate_gen6_wm(const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_scan_info *scan = &info->scan;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (ilo_dev_gen(dev) == ILO_GEN(6))
- assert(scan->earlyz_control == GEN7_EDSC_NORMAL);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 272:
- *
- * "This bit (Statistics Enable) must be disabled if either of these
- * bits is set: Depth Buffer Clear , Hierarchical Depth Buffer Resolve
- * Enable or Depth Buffer Resolve Enable."
- */
- if (scan->earlyz_op != ILO_STATE_RASTER_EARLYZ_NORMAL)
- assert(!scan->stats_enable);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 273:
- *
- * "If this field (Depth Buffer Resolve Enable) is enabled, the Depth
- * Buffer Clear and Hierarchical Depth Buffer Resolve Enable fields
- * must both be disabled."
- *
- * "If this field (Hierarchical Depth Buffer Resolve Enable) is
- * enabled, the Depth Buffer Clear and Depth Buffer Resolve Enable
- * fields must both be disabled."
- *
- * This is guaranteed.
- */
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 314-315:
- *
- * "Stencil buffer clear can be performed at the same time by enabling
- * Stencil Buffer Write Enable."
- *
- * "Note also that stencil buffer clear can be performed without depth
- * buffer clear."
- */
- if (scan->earlyz_stencil_clear) {
- assert(scan->earlyz_op == ILO_STATE_RASTER_EARLYZ_NORMAL ||
- scan->earlyz_op == ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR);
- }
-
- return true;
-}
-
-static bool
-raster_set_gen6_3dstate_wm(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- const struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_tri_info *tri = &info->tri;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- const enum gen_msrast_mode msrast =
- raster_setup_get_gen6_msrast_mode(dev, setup);
- /* only scan conversion states are set, as in Gen8+ */
- uint32_t dw4, dw5, dw6;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- if (!raster_validate_gen6_wm(dev, info))
- return false;
-
- dw4 = 0;
-
- if (scan->stats_enable)
- dw4 |= GEN6_WM_DW4_STATISTICS;
-
- switch (scan->earlyz_op) {
- case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR:
- dw4 |= GEN6_WM_DW4_DEPTH_CLEAR;
- break;
- case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE:
- dw4 |= GEN6_WM_DW4_DEPTH_RESOLVE;
- break;
- case ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE:
- dw4 |= GEN6_WM_DW4_HIZ_RESOLVE;
- break;
- default:
- if (scan->earlyz_stencil_clear)
- dw4 |= GEN6_WM_DW4_DEPTH_CLEAR;
- break;
- }
-
- dw5 = GEN6_WM_DW5_AA_LINE_CAP_1_0 | /* same as in 3DSTATE_SF */
- GEN6_WM_DW5_AA_LINE_WIDTH_2_0;
-
- if (tri->poly_stipple_enable)
- dw5 |= GEN6_WM_DW5_POLY_STIPPLE_ENABLE;
- if (line->stipple_enable)
- dw5 |= GEN6_WM_DW5_LINE_STIPPLE_ENABLE;
-
- dw6 = scan->zw_interp << GEN6_WM_DW6_ZW_INTERP__SHIFT |
- scan->barycentric_interps << GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT |
- GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT |
- msrast << GEN6_WM_DW6_MSRASTMODE__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->wm) >= 3);
- rs->wm[0] = dw4;
- rs->wm[1] = dw5;
- rs->wm[2] = dw6;
-
- return true;
-}
-
-static bool
-raster_set_gen8_3DSTATE_WM(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info,
- const struct ilo_state_raster_line_info *line)
-{
- const struct ilo_state_raster_tri_info *tri = &info->tri;
- const struct ilo_state_raster_setup_info *setup = &info->setup;
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- const enum gen_msrast_mode msrast =
- raster_setup_get_gen6_msrast_mode(dev, setup);
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!raster_validate_gen6_wm(dev, info))
- return false;
-
- dw1 = scan->earlyz_control << GEN7_WM_DW1_EDSC__SHIFT |
- scan->zw_interp << GEN7_WM_DW1_ZW_INTERP__SHIFT |
- scan->barycentric_interps << GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT |
- GEN7_WM_DW1_AA_LINE_CAP_1_0 | /* same as in 3DSTATE_SF */
- GEN7_WM_DW1_AA_LINE_WIDTH_2_0 |
- GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
-
- if (scan->stats_enable)
- dw1 |= GEN7_WM_DW1_STATISTICS;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8)) {
- switch (scan->earlyz_op) {
- case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR:
- dw1 |= GEN7_WM_DW1_LEGACY_DEPTH_CLEAR;
- break;
- case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE:
- dw1 |= GEN7_WM_DW1_LEGACY_DEPTH_RESOLVE;
- break;
- case ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE:
- dw1 |= GEN7_WM_DW1_LEGACY_HIZ_RESOLVE;
- break;
- default:
- if (scan->earlyz_stencil_clear)
- dw1 |= GEN7_WM_DW1_LEGACY_DEPTH_CLEAR;
- break;
- }
- }
-
- if (tri->poly_stipple_enable)
- dw1 |= GEN7_WM_DW1_POLY_STIPPLE_ENABLE;
- if (line->stipple_enable)
- dw1 |= GEN7_WM_DW1_LINE_STIPPLE_ENABLE;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8))
- dw1 |= msrast << GEN7_WM_DW1_MSRASTMODE__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->wm) >= 1);
- rs->wm[0] = dw1;
-
- return true;
-}
-
-static bool
-raster_set_gen8_3dstate_wm_hz_op(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- const struct ilo_state_raster_scan_info *scan = &info->scan;
- const enum gen_sample_count count =
- get_gen6_sample_count(dev, scan->sample_count);
- const uint32_t mask = (1 << scan->sample_count) - 1;
- uint32_t dw1, dw4;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- dw1 = count << GEN8_WM_HZ_DW1_NUM_SAMPLES__SHIFT;
-
- if (scan->earlyz_stencil_clear)
- dw1 |= GEN8_WM_HZ_DW1_STENCIL_CLEAR;
-
- switch (scan->earlyz_op) {
- case ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR:
- dw1 |= GEN8_WM_HZ_DW1_DEPTH_CLEAR;
- break;
- case ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE:
- dw1 |= GEN8_WM_HZ_DW1_DEPTH_RESOLVE;
- break;
- case ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE:
- dw1 |= GEN8_WM_HZ_DW1_HIZ_RESOLVE;
- break;
- default:
- break;
- }
-
- dw4 = (scan->sample_mask & mask) << GEN8_WM_HZ_DW4_SAMPLE_MASK__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(rs->wm) >= 3);
- rs->wm[1] = dw1;
- rs->wm[2] = dw4;
-
- return true;
-}
-
-static bool
-sample_pattern_get_gen6_packed_offsets(const struct ilo_dev *dev,
- uint8_t sample_count,
- const struct ilo_state_sample_pattern_offset_info *in,
- uint8_t *out)
-{
- uint8_t max_dist, i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- max_dist = 0;
- for (i = 0; i < sample_count; i++) {
- const int8_t dist_x = (int8_t) in[i].x - 8;
- const int8_t dist_y = (int8_t) in[i].y - 8;
- const uint8_t dist = dist_x * dist_x + dist_y * dist_y;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 305:
- *
- * "Programming Note: When programming the sample offsets (for
- * NUMSAMPLES_4 or _8 and MSRASTMODE_xxx_PATTERN), the order of the
- * samples 0 to 3 (or 7 for 8X) must have monotonically increasing
- * distance from the pixel center. This is required to get the
- * correct centroid computation in the device."
- */
- assert(dist >= max_dist);
- max_dist = dist;
-
- assert(in[i].x < 16);
- assert(in[i].y < 16);
-
- out[i] = in[i].x << 4 | in[i].y;
- }
-
- return true;
-}
-
-static bool
-line_stipple_set_gen6_3DSTATE_LINE_STIPPLE(struct ilo_state_line_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_line_stipple_info *info)
-{
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(info->repeat_count >= 1 && info->repeat_count <= 256);
-
- dw1 = info->pattern;
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- /* in U1.16 */
- const uint32_t inverse = 65536 / info->repeat_count;
- dw2 = inverse << GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT |
- info->repeat_count << GEN6_LINE_STIPPLE_DW2_REPEAT_COUNT__SHIFT;
- } else {
- /* in U1.13 */
- const uint16_t inverse = 8192 / info->repeat_count;
- dw2 = inverse << GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT |
- info->repeat_count << GEN6_LINE_STIPPLE_DW2_REPEAT_COUNT__SHIFT;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(stipple->stipple) >= 2);
- stipple->stipple[0] = dw1;
- stipple->stipple[1] = dw2;
-
- return true;
-}
-
-static bool
-sample_pattern_set_gen8_3DSTATE_SAMPLE_PATTERN(struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- const struct ilo_state_sample_pattern_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- STATIC_ASSERT(ARRAY_SIZE(pattern->pattern_1x) >= 1);
- STATIC_ASSERT(ARRAY_SIZE(pattern->pattern_2x) >= 2);
- STATIC_ASSERT(ARRAY_SIZE(pattern->pattern_4x) >= 4);
- STATIC_ASSERT(ARRAY_SIZE(pattern->pattern_8x) >= 8);
- STATIC_ASSERT(ARRAY_SIZE(pattern->pattern_16x) >= 16);
-
- return (sample_pattern_get_gen6_packed_offsets(dev, 1,
- info->pattern_1x, pattern->pattern_1x) &&
- sample_pattern_get_gen6_packed_offsets(dev, 2,
- info->pattern_2x, pattern->pattern_2x) &&
- sample_pattern_get_gen6_packed_offsets(dev, 4,
- info->pattern_4x, pattern->pattern_4x) &&
- sample_pattern_get_gen6_packed_offsets(dev, 8,
- info->pattern_8x, pattern->pattern_8x) &&
- sample_pattern_get_gen6_packed_offsets(dev, 16,
- info->pattern_16x, pattern->pattern_16x));
-
-}
-
-static bool
-poly_stipple_set_gen6_3DSTATE_POLY_STIPPLE_PATTERN(struct ilo_state_poly_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_poly_stipple_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- STATIC_ASSERT(ARRAY_SIZE(stipple->stipple) >= 32);
- memcpy(stipple->stipple, info->pattern, sizeof(info->pattern));
-
- return true;
-}
-
-bool
-ilo_state_raster_init(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- assert(ilo_is_zeroed(rs, sizeof(*rs)));
- return ilo_state_raster_set_info(rs, dev, info);
-}
-
-bool
-ilo_state_raster_init_for_rectlist(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- uint8_t sample_count,
- enum ilo_state_raster_earlyz_op earlyz_op,
- bool earlyz_stencil_clear)
-{
- struct ilo_state_raster_info info;
-
- memset(&info, 0, sizeof(info));
-
- info.clip.viewport_count = 1;
- info.setup.cv_is_rectangle = true;
- info.setup.msaa_enable = (sample_count > 1);
- info.scan.sample_count = sample_count;
- info.scan.sample_mask = ~0u;
- info.scan.earlyz_op = earlyz_op;
- info.scan.earlyz_stencil_clear = earlyz_stencil_clear;
-
- return ilo_state_raster_init(rs, dev, &info);
-}
-
-bool
-ilo_state_raster_set_info(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info)
-{
- struct ilo_state_raster_line_info line;
- bool ret = true;
-
- ret &= raster_set_gen6_3DSTATE_CLIP(rs, dev, info);
-
- raster_get_gen6_effective_line(dev, info, &line);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- ret &= raster_set_gen8_3DSTATE_SF(rs, dev, info, &line);
- ret &= raster_set_gen8_3DSTATE_RASTER(rs, dev, info, &line);
- } else {
- ret &= raster_set_gen7_3DSTATE_SF(rs, dev, info, &line);
- }
-
- ret &= raster_set_gen8_3DSTATE_MULTISAMPLE(rs, dev, info);
- ret &= raster_set_gen6_3DSTATE_SAMPLE_MASK(rs, dev, info);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- ret &= raster_set_gen8_3DSTATE_WM(rs, dev, info, &line);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- ret &= raster_set_gen8_3dstate_wm_hz_op(rs, dev, info);
- } else {
- ret &= raster_set_gen6_3dstate_wm(rs, dev, info, &line);
- }
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_raster_set_params(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_params_info *params)
-{
- const bool line_aa_enable = (rs->line_aa_enable &&
- raster_params_is_gen6_line_aa_allowed(dev, params));
- const int line_width = get_gen6_line_width(dev, params->line_width,
- line_aa_enable, rs->line_giq_enable);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* modify line AA enable */
- if (rs->line_aa_enable) {
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- if (line_aa_enable)
- rs->raster[0] |= GEN8_RASTER_DW1_AA_LINE_ENABLE;
- else
- rs->raster[0] &= ~GEN8_RASTER_DW1_AA_LINE_ENABLE;
- } else {
- if (line_aa_enable)
- rs->sf[1] |= GEN7_SF_DW2_AA_LINE_ENABLE;
- else
- rs->sf[1] &= ~GEN7_SF_DW2_AA_LINE_ENABLE;
- }
- }
-
- /* modify line width */
- rs->sf[1] = (rs->sf[1] & ~GEN7_SF_DW2_LINE_WIDTH__MASK) |
- line_width << GEN7_SF_DW2_LINE_WIDTH__SHIFT;
-
- /* modify point width */
- if (rs->sf[2] & GEN7_SF_DW3_USE_POINT_WIDTH) {
- const int point_width = get_gen6_point_width(dev, params->point_width);
-
- rs->sf[2] = (rs->sf[2] & ~GEN7_SF_DW3_POINT_WIDTH__MASK) |
- point_width << GEN7_SF_DW3_POINT_WIDTH__SHIFT;
- }
-
- /* modify depth offset */
- rs->raster[1] = fui(params->depth_offset_const);
- rs->raster[2] = fui(params->depth_offset_scale);
- rs->raster[3] = fui(params->depth_offset_clamp);
-
- return true;
-}
-
-void
-ilo_state_raster_full_delta(const struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- struct ilo_state_raster_delta *delta)
-{
- delta->dirty = ILO_STATE_RASTER_3DSTATE_CLIP |
- ILO_STATE_RASTER_3DSTATE_SF |
- ILO_STATE_RASTER_3DSTATE_MULTISAMPLE |
- ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK |
- ILO_STATE_RASTER_3DSTATE_WM |
- ILO_STATE_RASTER_3DSTATE_AA_LINE_PARAMETERS;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_RASTER |
- ILO_STATE_RASTER_3DSTATE_WM_HZ_OP;
- }
-}
-
-void
-ilo_state_raster_get_delta(const struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster *old,
- struct ilo_state_raster_delta *delta)
-{
- delta->dirty = 0;
-
- if (memcmp(rs->clip, old->clip, sizeof(rs->clip)))
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_CLIP;
-
- if (memcmp(rs->sf, old->sf, sizeof(rs->sf)))
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_SF;
-
- if (memcmp(rs->raster, old->raster, sizeof(rs->raster))) {
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_RASTER;
- else
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_SF;
- }
-
- if (memcmp(rs->sample, old->sample, sizeof(rs->sample))) {
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_MULTISAMPLE |
- ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK;
- }
-
- if (memcmp(rs->wm, old->wm, sizeof(rs->wm))) {
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_WM;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- delta->dirty |= ILO_STATE_RASTER_3DSTATE_WM_HZ_OP;
- }
-}
-
-bool
-ilo_state_sample_pattern_init(struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- const struct ilo_state_sample_pattern_info *info)
-{
- bool ret = true;
-
- ret &= sample_pattern_set_gen8_3DSTATE_SAMPLE_PATTERN(pattern, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_sample_pattern_init_default(struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev)
-{
- static const struct ilo_state_sample_pattern_info default_info = {
- .pattern_1x = {
- { 8, 8 },
- },
-
- .pattern_2x = {
- { 4, 4 }, { 12, 12 },
- },
-
- .pattern_4x = {
- { 6, 2 }, { 14, 6 }, { 2, 10 }, { 10, 14 },
- },
-
- /* \see brw_multisample_positions_8x */
- .pattern_8x = {
- { 7, 9 }, { 9, 13 }, { 11, 3 }, { 13, 11 },
- { 1, 7 }, { 5, 1 }, { 15, 5 }, { 3, 15 },
- },
-
- .pattern_16x = {
- { 8, 10 }, { 11, 8 }, { 5, 6 }, { 6, 4 },
- { 12, 11 }, { 13, 9 }, { 14, 7 }, { 10, 2 },
- { 4, 13 }, { 3, 3 }, { 7, 1 }, { 15, 5 },
- { 1, 12 }, { 9, 0 }, { 2, 14 }, { 0, 15 },
- },
- };
-
- return ilo_state_sample_pattern_init(pattern, dev, &default_info);
-}
-
-const uint8_t *
-ilo_state_sample_pattern_get_packed_offsets(const struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- uint8_t sample_count)
-{
- switch (sample_count) {
- case 1: return pattern->pattern_1x;
- case 2: return pattern->pattern_2x;
- case 4: return pattern->pattern_4x;
- case 8: return pattern->pattern_8x;
- case 16: return pattern->pattern_16x;
- default:
- assert(!"unknown sample count");
- return NULL;
- }
-}
-
-void
-ilo_state_sample_pattern_get_offset(const struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- uint8_t sample_count, uint8_t sample_index,
- uint8_t *x, uint8_t *y)
-{
- const const uint8_t *packed =
- ilo_state_sample_pattern_get_packed_offsets(pattern, dev, sample_count);
-
- assert(sample_index < sample_count);
-
- *x = (packed[sample_index] >> 4) & 0xf;
- *y = packed[sample_index] & 0xf;
-}
-
-/**
- * No need to initialize first.
- */
-bool
-ilo_state_line_stipple_set_info(struct ilo_state_line_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_line_stipple_info *info)
-{
- bool ret = true;
-
- ret &= line_stipple_set_gen6_3DSTATE_LINE_STIPPLE(stipple,
- dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-/**
- * No need to initialize first.
- */
-bool
-ilo_state_poly_stipple_set_info(struct ilo_state_poly_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_poly_stipple_info *info)
-{
- bool ret = true;
-
- ret &= poly_stipple_set_gen6_3DSTATE_POLY_STIPPLE_PATTERN(stipple,
- dev, info);
-
- assert(ret);
-
- return ret;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_state_raster.h b/src/gallium/drivers/ilo/core/ilo_state_raster.h
deleted file mode 100644
index fc90b49cfc3..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_raster.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_RASTER_H
-#define ILO_STATE_RASTER_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-enum ilo_state_raster_dirty_bits {
- ILO_STATE_RASTER_3DSTATE_CLIP = (1 << 0),
- ILO_STATE_RASTER_3DSTATE_SF = (1 << 1),
- ILO_STATE_RASTER_3DSTATE_RASTER = (1 << 2),
- ILO_STATE_RASTER_3DSTATE_MULTISAMPLE = (1 << 3),
- ILO_STATE_RASTER_3DSTATE_SAMPLE_MASK = (1 << 4),
- ILO_STATE_RASTER_3DSTATE_WM = (1 << 5),
- ILO_STATE_RASTER_3DSTATE_WM_HZ_OP = (1 << 6),
- ILO_STATE_RASTER_3DSTATE_AA_LINE_PARAMETERS = (1 << 7),
-};
-
-enum ilo_state_raster_earlyz_op {
- ILO_STATE_RASTER_EARLYZ_NORMAL,
- ILO_STATE_RASTER_EARLYZ_DEPTH_CLEAR,
- ILO_STATE_RASTER_EARLYZ_DEPTH_RESOLVE,
- ILO_STATE_RASTER_EARLYZ_HIZ_RESOLVE,
-};
-
-/**
- * VUE readback, VertexClipTest, ClipDetermination, and primitive output.
- */
-struct ilo_state_raster_clip_info {
- bool clip_enable;
- /* CL_INVOCATION_COUNT and CL_PRIMITIVES_COUNT */
- bool stats_enable;
-
- uint8_t viewport_count;
- bool force_rtaindex_zero;
-
- /* these should be mutually exclusive */
- uint8_t user_cull_enables;
- uint8_t user_clip_enables;
-
- bool gb_test_enable;
- bool xy_test_enable;
-
- /* far/near must be enabled together prior to Gen9 */
- bool z_far_enable;
- bool z_near_enable;
- bool z_near_zero;
-};
-
-/**
- * Primitive assembly, viewport transformation, scissoring, MSAA, etc.
- */
-struct ilo_state_raster_setup_info {
- bool cv_is_rectangle;
-
- bool first_vertex_provoking;
- bool viewport_transform;
-
- bool scissor_enable;
-
- /* MSAA enables for lines and non-lines */
- bool msaa_enable;
- bool line_msaa_enable;
-};
-
-/**
- * 3DOBJ_POINT rasterization rules.
- */
-struct ilo_state_raster_point_info {
- /* ignored when msaa_enable is set */
- bool aa_enable;
-
- bool programmable_width;
-};
-
-/**
- * 3DOBJ_LINE rasterization rules.
- */
-struct ilo_state_raster_line_info {
- /* ignored when line_msaa_enable is set */
- bool aa_enable;
-
- /* ignored when line_msaa_enable or aa_enable is set */
- bool stipple_enable;
- bool giq_enable;
- bool giq_last_pixel;
-};
-
-/**
- * 3DOBJ_TRIANGLE rasterization rules.
- */
-struct ilo_state_raster_tri_info {
- enum gen_front_winding front_winding;
- enum gen_cull_mode cull_mode;
- enum gen_fill_mode fill_mode_front;
- enum gen_fill_mode fill_mode_back;
-
- enum gen_depth_format depth_offset_format;
- bool depth_offset_solid;
- bool depth_offset_wireframe;
- bool depth_offset_point;
-
- bool poly_stipple_enable;
-};
-
-/**
- * Scan conversion.
- */
-struct ilo_state_raster_scan_info {
- /* PS_DEPTH_COUNT and PS_INVOCATION_COUNT */
- bool stats_enable;
-
- uint8_t sample_count;
-
- /* pixel location for non-MSAA or 1x-MSAA */
- enum gen_pixel_location pixloc;
-
- uint32_t sample_mask;
-
- /* interpolations */
- enum gen_zw_interp zw_interp;
- uint8_t barycentric_interps;
-
- /* Gen7+ only */
- enum gen_edsc_mode earlyz_control;
- enum ilo_state_raster_earlyz_op earlyz_op;
- bool earlyz_stencil_clear;
-};
-
-/**
- * Raster parameters.
- */
-struct ilo_state_raster_params_info {
- bool any_integer_rt;
- bool hiz_enable;
-
- float point_width;
- float line_width;
-
- /* const term will be scaled by 'r' */
- float depth_offset_const;
- float depth_offset_scale;
- float depth_offset_clamp;
-};
-
-struct ilo_state_raster_info {
- struct ilo_state_raster_clip_info clip;
- struct ilo_state_raster_setup_info setup;
- struct ilo_state_raster_point_info point;
- struct ilo_state_raster_line_info line;
- struct ilo_state_raster_tri_info tri;
- struct ilo_state_raster_scan_info scan;
-
- struct ilo_state_raster_params_info params;
-};
-
-struct ilo_state_raster {
- uint32_t clip[3];
- uint32_t sf[3];
- uint32_t raster[4];
- uint32_t sample[2];
- uint32_t wm[3];
-
- bool line_aa_enable;
- bool line_giq_enable;
-};
-
-struct ilo_state_raster_delta {
- uint32_t dirty;
-};
-
-struct ilo_state_sample_pattern_offset_info {
- /* in U0.4 */
- uint8_t x;
- uint8_t y;
-};
-
-struct ilo_state_sample_pattern_info {
- struct ilo_state_sample_pattern_offset_info pattern_1x[1];
- struct ilo_state_sample_pattern_offset_info pattern_2x[2];
- struct ilo_state_sample_pattern_offset_info pattern_4x[4];
- struct ilo_state_sample_pattern_offset_info pattern_8x[8];
- struct ilo_state_sample_pattern_offset_info pattern_16x[16];
-};
-
-struct ilo_state_sample_pattern {
- uint8_t pattern_1x[1];
- uint8_t pattern_2x[2];
- uint8_t pattern_4x[4];
- uint8_t pattern_8x[8];
- uint8_t pattern_16x[16];
-};
-
-struct ilo_state_line_stipple_info {
- uint16_t pattern;
- uint16_t repeat_count;
-};
-
-struct ilo_state_line_stipple {
- uint32_t stipple[2];
-};
-
-struct ilo_state_poly_stipple_info {
- uint32_t pattern[32];
-};
-
-struct ilo_state_poly_stipple {
- uint32_t stipple[32];
-};
-
-bool
-ilo_state_raster_init(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info);
-
-bool
-ilo_state_raster_init_for_rectlist(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- uint8_t sample_count,
- enum ilo_state_raster_earlyz_op earlyz_op,
- bool earlyz_stencil_clear);
-
-bool
-ilo_state_raster_set_info(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_info *info);
-
-bool
-ilo_state_raster_set_params(struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster_params_info *params);
-
-void
-ilo_state_raster_full_delta(const struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- struct ilo_state_raster_delta *delta);
-
-void
-ilo_state_raster_get_delta(const struct ilo_state_raster *rs,
- const struct ilo_dev *dev,
- const struct ilo_state_raster *old,
- struct ilo_state_raster_delta *delta);
-
-bool
-ilo_state_sample_pattern_init(struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- const struct ilo_state_sample_pattern_info *info);
-
-bool
-ilo_state_sample_pattern_init_default(struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev);
-
-const uint8_t *
-ilo_state_sample_pattern_get_packed_offsets(const struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- uint8_t sample_count);
-
-void
-ilo_state_sample_pattern_get_offset(const struct ilo_state_sample_pattern *pattern,
- const struct ilo_dev *dev,
- uint8_t sample_count, uint8_t sample_index,
- uint8_t *x, uint8_t *y);
-bool
-ilo_state_line_stipple_set_info(struct ilo_state_line_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_line_stipple_info *info);
-
-bool
-ilo_state_poly_stipple_set_info(struct ilo_state_poly_stipple *stipple,
- const struct ilo_dev *dev,
- const struct ilo_state_poly_stipple_info *info);
-
-#endif /* ILO_STATE_RASTER_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_state_sampler.c b/src/gallium/drivers/ilo/core/ilo_state_sampler.c
deleted file mode 100644
index 3787f684fe8..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_sampler.c
+++ /dev/null
@@ -1,742 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "util/u_half.h"
-
-#include "ilo_debug.h"
-#include "ilo_state_surface.h"
-#include "ilo_state_sampler.h"
-
-static bool
-sampler_validate_gen6_non_normalized(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- const enum gen_texcoord_mode addr_ctrls[3] = {
- info->tcx_ctrl, info->tcy_ctrl, info->tcz_ctrl,
- };
- int i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 98:
- *
- * "The following state must be set as indicated if this field
- * (Non-normalized Coordinate Enable) is enabled:
- *
- * - TCX/Y/Z Address Control Mode must be TEXCOORDMODE_CLAMP,
- * TEXCOORDMODE_HALF_BORDER, or TEXCOORDMODE_CLAMP_BORDER.
- * - Surface Type must be SURFTYPE_2D or SURFTYPE_3D.
- * - Mag Mode Filter must be MAPFILTER_NEAREST or
- * MAPFILTER_LINEAR.
- * - Min Mode Filter must be MAPFILTER_NEAREST or
- * MAPFILTER_LINEAR.
- * - Mip Mode Filter must be MIPFILTER_NONE.
- * - Min LOD must be 0.
- * - Max LOD must be 0.
- * - MIP Count must be 0.
- * - Surface Min LOD must be 0.
- * - Texture LOD Bias must be 0."
- */
- for (i = 0; i < 3; i++) {
- switch (addr_ctrls[i]) {
- case GEN6_TEXCOORDMODE_CLAMP:
- case GEN6_TEXCOORDMODE_CLAMP_BORDER:
- case GEN8_TEXCOORDMODE_HALF_BORDER:
- break;
- default:
- assert(!"bad non-normalized coordinate wrap mode");
- break;
- }
- }
-
- assert(info->mip_filter == GEN6_MIPFILTER_NONE);
-
- assert((info->min_filter == GEN6_MAPFILTER_NEAREST ||
- info->min_filter == GEN6_MAPFILTER_LINEAR) &&
- (info->mag_filter == GEN6_MAPFILTER_NEAREST ||
- info->mag_filter == GEN6_MAPFILTER_LINEAR));
-
- assert(info->min_lod == 0.0f &&
- info->max_lod == 0.0f &&
- info->lod_bias == 0.0f);
-
- return true;
-}
-
-static bool
-sampler_validate_gen6_sampler(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->non_normalized &&
- !sampler_validate_gen6_non_normalized(dev, info))
- return false;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8)) {
- assert(info->tcx_ctrl != GEN8_TEXCOORDMODE_HALF_BORDER &&
- info->tcy_ctrl != GEN8_TEXCOORDMODE_HALF_BORDER &&
- info->tcz_ctrl != GEN8_TEXCOORDMODE_HALF_BORDER);
- }
-
- return true;
-}
-
-static uint32_t
-sampler_get_gen6_integer_filters(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 103:
- *
- * "MIPFILTER_LINEAR is not supported for surface formats that do not
- * support "Sampling Engine Filtering" as indicated in the Surface
- * Formats table unless using the sample_c message type."
- *
- * "Only MAPFILTER_NEAREST is supported for surface formats that do not
- * support "Sampling Engine Filtering" as indicated in the Surface
- * Formats table unless using the sample_c message type.
- */
- const enum gen_mip_filter mip_filter =
- (info->mip_filter == GEN6_MIPFILTER_LINEAR) ?
- GEN6_MIPFILTER_NEAREST : info->mip_filter;
- const enum gen_map_filter min_filter = GEN6_MAPFILTER_NEAREST;
- const enum gen_map_filter mag_filter = GEN6_MAPFILTER_NEAREST;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return mip_filter << GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT |
- mag_filter << GEN6_SAMPLER_DW0_MAG_FILTER__SHIFT |
- min_filter << GEN6_SAMPLER_DW0_MIN_FILTER__SHIFT;
-}
-
-static uint32_t
-sampler_get_gen6_3d_filters(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- const enum gen_mip_filter mip_filter = info->mip_filter;
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 103:
- *
- * "Only MAPFILTER_NEAREST and MAPFILTER_LINEAR are supported for
- * surfaces of type SURFTYPE_3D."
- */
- const enum gen_map_filter min_filter =
- (info->min_filter == GEN6_MAPFILTER_NEAREST ||
- info->min_filter == GEN6_MAPFILTER_LINEAR) ?
- info->min_filter : GEN6_MAPFILTER_LINEAR;
- const enum gen_map_filter mag_filter =
- (info->mag_filter == GEN6_MAPFILTER_NEAREST ||
- info->mag_filter == GEN6_MAPFILTER_LINEAR) ?
- info->mag_filter : GEN6_MAPFILTER_LINEAR;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return mip_filter << GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT |
- mag_filter << GEN6_SAMPLER_DW0_MAG_FILTER__SHIFT |
- min_filter << GEN6_SAMPLER_DW0_MIN_FILTER__SHIFT;
-}
-
-static uint32_t
-get_gen6_addr_controls(const struct ilo_dev *dev,
- enum gen_texcoord_mode tcx_ctrl,
- enum gen_texcoord_mode tcy_ctrl,
- enum gen_texcoord_mode tcz_ctrl)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- return tcx_ctrl << GEN7_SAMPLER_DW3_U_WRAP__SHIFT |
- tcy_ctrl << GEN7_SAMPLER_DW3_V_WRAP__SHIFT |
- tcz_ctrl << GEN7_SAMPLER_DW3_R_WRAP__SHIFT;
- } else {
- return tcx_ctrl << GEN6_SAMPLER_DW1_U_WRAP__SHIFT |
- tcy_ctrl << GEN6_SAMPLER_DW1_V_WRAP__SHIFT |
- tcz_ctrl << GEN6_SAMPLER_DW1_R_WRAP__SHIFT;
- }
-}
-
-static uint32_t
-sampler_get_gen6_1d_addr_controls(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- const enum gen_texcoord_mode tcx_ctrl =
- (info->tcx_ctrl == GEN6_TEXCOORDMODE_CUBE) ?
- GEN6_TEXCOORDMODE_CLAMP : info->tcx_ctrl;
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 100:
- *
- * "If this field (TCY Address Control Mode) is set to
- * TEXCOORDMODE_CLAMP_BORDER or TEXCOORDMODE_HALF_BORDER and a 1D
- * surface is sampled, incorrect blending with the border color in the
- * vertical direction may occur."
- */
- const enum gen_texcoord_mode tcy_ctrl = GEN6_TEXCOORDMODE_CLAMP;
- const enum gen_texcoord_mode tcz_ctrl = GEN6_TEXCOORDMODE_CLAMP;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return get_gen6_addr_controls(dev, tcx_ctrl, tcy_ctrl, tcz_ctrl);
-}
-
-static uint32_t
-sampler_get_gen6_2d_3d_addr_controls(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- const enum gen_texcoord_mode tcx_ctrl =
- (info->tcx_ctrl == GEN6_TEXCOORDMODE_CUBE) ?
- GEN6_TEXCOORDMODE_CLAMP : info->tcx_ctrl;
- const enum gen_texcoord_mode tcy_ctrl =
- (info->tcy_ctrl == GEN6_TEXCOORDMODE_CUBE) ?
- GEN6_TEXCOORDMODE_CLAMP : info->tcy_ctrl;
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 108:
- *
- * "[DevSNB]: if this field (TCZ Address Control Mode) is set to
- * TEXCOORDMODE_CLAMP_BORDER samples outside the map will clamp to 0
- * instead of boarder color"
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 100:
- *
- * "If this field is set to TEXCOORDMODE_CLAMP_BORDER for 3D maps on
- * formats without an alpha channel, samples straddling the map in the
- * Z direction may have their alpha channels off by 1."
- *
- * Do we want to do something here?
- */
- const enum gen_texcoord_mode tcz_ctrl =
- (info->tcz_ctrl == GEN6_TEXCOORDMODE_CUBE) ?
- GEN6_TEXCOORDMODE_CLAMP : info->tcz_ctrl;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return get_gen6_addr_controls(dev, tcx_ctrl, tcy_ctrl, tcz_ctrl);
-}
-
-static uint32_t
-sampler_get_gen6_cube_addr_controls(const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 99:
- *
- * "When using cube map texture coordinates, only TEXCOORDMODE_CLAMP
- * and TEXCOORDMODE_CUBE settings are valid, and each TC component
- * must have the same Address Control mode.
- *
- * When TEXCOORDMODE_CUBE is not used accessing a cube map, the map's
- * Cube Face Enable field must be programmed to 111111b (all faces
- * enabled)."
- *
- * From the Haswell PRM, volume 2d, page 278:
- *
- * "When using cube map texture coordinates, each TC component must
- * have the same Address Control Mode.
- *
- * When TEXCOORDMODE_CUBE is not used accessing a cube map, the map's
- * Cube Face Enable field must be programmed to 111111b (all faces
- * enabled)."
- *
- * We always enable all cube faces and only need to make sure all address
- * control modes are the same.
- */
- const enum gen_texcoord_mode tcx_ctrl =
- (ilo_dev_gen(dev) >= ILO_GEN(7.5) ||
- info->tcx_ctrl == GEN6_TEXCOORDMODE_CUBE ||
- info->tcx_ctrl == GEN6_TEXCOORDMODE_CLAMP) ?
- info->tcx_ctrl : GEN6_TEXCOORDMODE_CLAMP;
- const enum gen_texcoord_mode tcy_ctrl = tcx_ctrl;
- const enum gen_texcoord_mode tcz_ctrl = tcx_ctrl;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return get_gen6_addr_controls(dev, tcx_ctrl, tcy_ctrl, tcz_ctrl);
-}
-
-static uint16_t
-get_gen6_lod_bias(const struct ilo_dev *dev, float bias)
-{
- /* [-16.0, 16.0) in S4.6 or S4.8 */
- const int fbits = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 8 : 6;
- const float max = 16.0f;
- const float scale = (float) (1 << fbits);
- const int mask = (1 << (1 + 4 + fbits)) - 1;
- const int scaled_max = (16 << fbits) - 1;
- int scaled;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (bias > max)
- bias = max;
- else if (bias < -max)
- bias = -max;
-
- scaled = (int) (bias * scale);
- if (scaled > scaled_max)
- scaled = scaled_max;
-
- return (scaled & mask);
-}
-
-static uint16_t
-get_gen6_lod_clamp(const struct ilo_dev *dev, float clamp)
-{
- /* [0.0, 13.0] in U4.6 or [0.0, 14.0] in U4.8 */
- const int fbits = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 8 : 6;
- const float max = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 14.0f : 13.0f;
- const float scale = (float) (1 << fbits);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (clamp > max)
- clamp = max;
- else if (clamp < 0.0f)
- clamp = 0.0f;
-
- return (int) (clamp * scale);
-}
-
-static bool
-sampler_set_gen6_SAMPLER_STATE(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- uint16_t lod_bias, max_lod, min_lod;
- uint32_t dw0, dw1, dw3;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!sampler_validate_gen6_sampler(dev, info))
- return false;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 15:
- *
- * "The per-pixel LOD is computed in an implementation-dependent manner
- * and approximates the log2 of the texel/pixel ratio at the given
- * pixel. The computation is typically based on the differential
- * texel-space distances associated with a one-pixel differential
- * distance along the screen x- and y-axes. These texel-space
- * distances are computed by evaluating neighboring pixel texture
- * coordinates, these coordinates being in units of texels on the base
- * MIP level (multiplied by the corresponding surface size in
- * texels)."
- *
- * Judging from the LOD computation pseudocode on page 16-18, the "base MIP
- * level" should be given by SurfMinLod. To summarize, for the "sample"
- * message,
- *
- * 1) LOD is set to log2(texel/pixel ratio). The number of texels is
- * measured against level SurfMinLod.
- * 2) Bias is added to LOD.
- * 3) if pre-clamp is enabled, LOD is clamped to [MinLod, MaxLod] first
- * 4) LOD is compared with Base to determine whether magnification or
- * minification is needed.
- * 5) If magnification is needed, or no mipmapping is requested, LOD is
- * set to floor(MinLod).
- * 6) LOD is clamped to [0, MIPCnt], and SurfMinLod is added to LOD.
- *
- * As an example, we could set SurfMinLod to GL_TEXTURE_BASE_LEVEL and Base
- * to 0 to match GL. But GL expects LOD to be set to 0, instead of
- * floor(MinLod), in 5). Since this is only an issue when MinLod is
- * greater than or equal to one, and, with Base being 0, a non-zero MinLod
- * implies minification, we only need to deal with the case when mipmapping
- * is disabled. We can thus do:
- *
- * if (MipFilter == MIPFILTER_NONE && MinLod) {
- * MinLod = 0;
- * MagFilter = MinFilter;
- * }
- */
-
- lod_bias = get_gen6_lod_bias(dev, info->lod_bias);
- min_lod = get_gen6_lod_clamp(dev, info->min_lod);
- max_lod = get_gen6_lod_clamp(dev, info->max_lod);
-
- dw0 = GEN6_SAMPLER_DW0_LOD_PRECLAMP_ENABLE |
- 0 << GEN6_SAMPLER_DW0_BASE_LOD__SHIFT |
- info->mip_filter << GEN6_SAMPLER_DW0_MIP_FILTER__SHIFT |
- info->mag_filter << GEN6_SAMPLER_DW0_MAG_FILTER__SHIFT |
- info->min_filter << GEN6_SAMPLER_DW0_MIN_FILTER__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- dw0 |= GEN7_SAMPLER_DW0_BORDER_COLOR_MODE_DX10_OGL |
- lod_bias << GEN7_SAMPLER_DW0_LOD_BIAS__SHIFT;
-
- if (info->min_filter == GEN6_MAPFILTER_ANISOTROPIC ||
- info->mag_filter == GEN6_MAPFILTER_ANISOTROPIC)
- dw0 |= GEN7_SAMPLER_DW0_ANISO_ALGO_EWA;
- } else {
- dw0 |= lod_bias << GEN6_SAMPLER_DW0_LOD_BIAS__SHIFT |
- info->shadow_func << GEN6_SAMPLER_DW0_SHADOW_FUNC__SHIFT;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 102:
- *
- * "(Min and Mag State Not Equal) Must be set to 1 if any of the
- * following are true:
- *
- * - Mag Mode Filter and Min Mode Filter are not the same
- * - Address Rounding Enable: U address mag filter and U address
- * min filter are not the same
- * - Address Rounding Enable: V address mag filter and V address
- * min filter are not the same
- * - Address Rounding Enable: R address mag filter and R address
- * min filter are not the same"
- *
- * We set address rounding for U, V, and R uniformly. Only need to
- * check the filters.
- */
- if (info->min_filter != info->mag_filter)
- dw0 |= GEN6_SAMPLER_DW0_MIN_MAG_NOT_EQUAL;
- }
-
- dw1 = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 96:
- *
- * "This field (Cube Surface Control Mode) must be set to
- * CUBECTRLMODE_PROGRAMMED"
- */
- dw1 |= min_lod << GEN7_SAMPLER_DW1_MIN_LOD__SHIFT |
- max_lod << GEN7_SAMPLER_DW1_MAX_LOD__SHIFT |
- info->shadow_func << GEN7_SAMPLER_DW1_SHADOW_FUNC__SHIFT |
- GEN7_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED;
- } else {
- dw1 |= min_lod << GEN6_SAMPLER_DW1_MIN_LOD__SHIFT |
- max_lod << GEN6_SAMPLER_DW1_MAX_LOD__SHIFT |
- GEN6_SAMPLER_DW1_CUBECTRLMODE_PROGRAMMED |
- info->tcx_ctrl << GEN6_SAMPLER_DW1_U_WRAP__SHIFT |
- info->tcy_ctrl << GEN6_SAMPLER_DW1_V_WRAP__SHIFT |
- info->tcz_ctrl << GEN6_SAMPLER_DW1_R_WRAP__SHIFT;
- }
-
- dw3 = info->max_anisotropy << GEN6_SAMPLER_DW3_MAX_ANISO__SHIFT;
-
- /* round the coordinates for linear filtering */
- if (info->min_filter != GEN6_MAPFILTER_NEAREST) {
- dw3 |= GEN6_SAMPLER_DW3_U_MIN_ROUND |
- GEN6_SAMPLER_DW3_V_MIN_ROUND |
- GEN6_SAMPLER_DW3_R_MIN_ROUND;
- }
- if (info->mag_filter != GEN6_MAPFILTER_NEAREST) {
- dw3 |= GEN6_SAMPLER_DW3_U_MAG_ROUND |
- GEN6_SAMPLER_DW3_V_MAG_ROUND |
- GEN6_SAMPLER_DW3_R_MAG_ROUND;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- dw3 |= GEN7_SAMPLER_DW3_TRIQUAL_FULL |
- info->tcx_ctrl << GEN7_SAMPLER_DW3_U_WRAP__SHIFT |
- info->tcy_ctrl << GEN7_SAMPLER_DW3_V_WRAP__SHIFT |
- info->tcz_ctrl << GEN7_SAMPLER_DW3_R_WRAP__SHIFT;
-
- if (info->non_normalized)
- dw3 |= GEN7_SAMPLER_DW3_NON_NORMALIZED_COORD;
- } else {
- if (info->non_normalized)
- dw3 |= GEN6_SAMPLER_DW3_NON_NORMALIZED_COORD;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(sampler->sampler) >= 3);
- sampler->sampler[0] = dw0;
- sampler->sampler[1] = dw1;
- sampler->sampler[2] = dw3;
-
- sampler->filter_integer = sampler_get_gen6_integer_filters(dev, info);
- sampler->filter_3d = sampler_get_gen6_3d_filters(dev, info);
- sampler->addr_ctrl_1d = sampler_get_gen6_1d_addr_controls(dev, info);
- sampler->addr_ctrl_2d_3d = sampler_get_gen6_2d_3d_addr_controls(dev, info);
- sampler->addr_ctrl_cube = sampler_get_gen6_cube_addr_controls(dev, info);
-
- sampler->non_normalized = info->non_normalized;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 21:
- *
- * "[DevSNB] Errata: Incorrect behavior is observed in cases where the
- * min and mag mode filters are different and SurfMinLOD is nonzero.
- * The determination of MagMode uses the following equation instead of
- * the one in the above pseudocode:
- *
- * MagMode = (LOD + SurfMinLOD - Base <= 0)"
- *
- * As a way to work around that, request Base to be set to SurfMinLod.
- */
- if (ilo_dev_gen(dev) == ILO_GEN(6) &&
- info->min_filter != info->mag_filter)
- sampler->base_to_surf_min_lod = true;
-
- return true;
-}
-
-static bool
-sampler_border_set_gen6_SAMPLER_BORDER_COLOR_STATE(struct ilo_state_sampler_border *border,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_border_info *info)
-{
- uint32_t dw[12];
- float rgba[4];
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 117:
- *
- * "For ([DevSNB]), if border color is used, all formats must be
- * provided. Hardware will choose the appropriate format based on
- * Surface Format and Texture Border Color Mode. The values
- * represented by each format should be the same (other than being
- * subject to range-based clamping and precision) to avoid unexpected
- * behavior."
- *
- * XXX We do not honor info->is_integer yet.
- */
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /* make a copy so that we can clamp for SNORM and UNORM */
- memcpy(rgba, info->rgba.f, sizeof(rgba));
-
- /* IEEE_FP */
- dw[1] = fui(rgba[0]);
- dw[2] = fui(rgba[1]);
- dw[3] = fui(rgba[2]);
- dw[4] = fui(rgba[3]);
-
- /* FLOAT_16 */
- dw[5] = util_float_to_half(rgba[0]) |
- util_float_to_half(rgba[1]) << 16;
- dw[6] = util_float_to_half(rgba[2]) |
- util_float_to_half(rgba[3]) << 16;
-
- /* clamp to [-1.0f, 1.0f] */
- rgba[0] = CLAMP(rgba[0], -1.0f, 1.0f);
- rgba[1] = CLAMP(rgba[1], -1.0f, 1.0f);
- rgba[2] = CLAMP(rgba[2], -1.0f, 1.0f);
- rgba[3] = CLAMP(rgba[3], -1.0f, 1.0f);
-
- /* SNORM16 */
- dw[9] = (int16_t) util_iround(rgba[0] * 32767.0f) |
- (int16_t) util_iround(rgba[1] * 32767.0f) << 16;
- dw[10] = (int16_t) util_iround(rgba[2] * 32767.0f) |
- (int16_t) util_iround(rgba[3] * 32767.0f) << 16;
-
- /* SNORM8 */
- dw[11] = (int8_t) util_iround(rgba[0] * 127.0f) |
- (int8_t) util_iround(rgba[1] * 127.0f) << 8 |
- (int8_t) util_iround(rgba[2] * 127.0f) << 16 |
- (int8_t) util_iround(rgba[3] * 127.0f) << 24;
-
- /* clamp to [0.0f, 1.0f] */
- rgba[0] = CLAMP(rgba[0], 0.0f, 1.0f);
- rgba[1] = CLAMP(rgba[1], 0.0f, 1.0f);
- rgba[2] = CLAMP(rgba[2], 0.0f, 1.0f);
- rgba[3] = CLAMP(rgba[3], 0.0f, 1.0f);
-
- /* UNORM8 */
- dw[0] = (uint8_t) util_iround(rgba[0] * 255.0f) |
- (uint8_t) util_iround(rgba[1] * 255.0f) << 8 |
- (uint8_t) util_iround(rgba[2] * 255.0f) << 16 |
- (uint8_t) util_iround(rgba[3] * 255.0f) << 24;
-
- /* UNORM16 */
- dw[7] = (uint16_t) util_iround(rgba[0] * 65535.0f) |
- (uint16_t) util_iround(rgba[1] * 65535.0f) << 16;
- dw[8] = (uint16_t) util_iround(rgba[2] * 65535.0f) |
- (uint16_t) util_iround(rgba[3] * 65535.0f) << 16;
-
- STATIC_ASSERT(ARRAY_SIZE(border->color) >= 12);
- memcpy(border->color, dw, sizeof(dw));
-
- return true;
-}
-
-static bool
-sampler_border_set_gen7_SAMPLER_BORDER_COLOR_STATE(struct ilo_state_sampler_border *border,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_border_info *info)
-{
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 116:
- *
- * "In DX10/OGL mode, the format of the border color is
- * R32G32B32A32_FLOAT, regardless of the surface format chosen."
- *
- * From the Haswell PRM, volume 2d, page 240:
- *
- * "So, SW will have to program the table in SAMPLER_BORDER_COLOR_STATE
- * at offsets DWORD16 to 19, as per the integer surface format type."
- *
- * From the Broadwell PRM, volume 2d, page 297:
- *
- * "DX10/OGL mode: the format of the border color depends on the format
- * of the surface being sampled. If the map format is UINT, then the
- * border color format is R32G32B32A32_UINT. If the map format is
- * SINT, then the border color format is R32G32B32A32_SINT. Otherwise,
- * the border color format is R32G32B32A32_FLOAT."
- *
- * XXX every Gen is different
- */
-
- STATIC_ASSERT(ARRAY_SIZE(border->color) >= 4);
- memcpy(border->color, info->rgba.f, sizeof(info->rgba.f));
-
- return true;
-}
-
-bool
-ilo_state_sampler_init(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(sampler, sizeof(*sampler)));
-
- ret &= sampler_set_gen6_SAMPLER_STATE(sampler, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_sampler_init_disabled(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(ilo_is_zeroed(sampler, sizeof(*sampler)));
-
- sampler->sampler[0] = GEN6_SAMPLER_DW0_DISABLE;
- sampler->sampler[1] = 0;
- sampler->sampler[2] = 0;
-
- return true;
-}
-
-/**
- * Modify \p sampler to work with \p surf. There will be loss of information.
- * Callers should make a copy of the orignal sampler first.
- */
-bool
-ilo_state_sampler_set_surface(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev,
- const struct ilo_state_surface *surf)
-{
- uint32_t addr_ctrl;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (sampler->non_normalized) {
- /* see sampler_validate_gen6_non_normalized() */
- assert(surf->type == GEN6_SURFTYPE_2D ||
- surf->type == GEN6_SURFTYPE_3D);
- assert(!surf->min_lod && !surf->mip_count);
- }
-
- if (sampler->base_to_surf_min_lod) {
- const uint8_t base = surf->min_lod << GEN6_SAMPLER_DW0_BASE_LOD__RADIX;
-
- sampler->sampler[0] =
- (sampler->sampler[0] & ~GEN6_SAMPLER_DW0_BASE_LOD__MASK) |
- base << GEN6_SAMPLER_DW0_BASE_LOD__SHIFT;
- }
-
- if (surf->is_integer || surf->type == GEN6_SURFTYPE_3D) {
- const uint32_t mask = (GEN6_SAMPLER_DW0_MIP_FILTER__MASK |
- GEN6_SAMPLER_DW0_MIN_FILTER__MASK |
- GEN6_SAMPLER_DW0_MAG_FILTER__MASK);
- const uint32_t filter = (surf->is_integer) ?
- sampler->filter_integer : sampler->filter_3d;
-
- assert((filter & mask) == filter);
- sampler->sampler[0] = (sampler->sampler[0] & ~mask) |
- filter;
- }
-
- switch (surf->type) {
- case GEN6_SURFTYPE_1D:
- addr_ctrl = sampler->addr_ctrl_1d;
- break;
- case GEN6_SURFTYPE_2D:
- case GEN6_SURFTYPE_3D:
- addr_ctrl = sampler->addr_ctrl_2d_3d;
- break;
- case GEN6_SURFTYPE_CUBE:
- addr_ctrl = sampler->addr_ctrl_cube;
- break;
- default:
- assert(!"unexpected surface type");
- addr_ctrl = 0;
- break;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- const uint32_t mask = (GEN7_SAMPLER_DW3_U_WRAP__MASK |
- GEN7_SAMPLER_DW3_V_WRAP__MASK |
- GEN7_SAMPLER_DW3_R_WRAP__MASK);
-
- assert((addr_ctrl & mask) == addr_ctrl);
- sampler->sampler[2] = (sampler->sampler[2] & ~mask) |
- addr_ctrl;
- } else {
- const uint32_t mask = (GEN6_SAMPLER_DW1_U_WRAP__MASK |
- GEN6_SAMPLER_DW1_V_WRAP__MASK |
- GEN6_SAMPLER_DW1_R_WRAP__MASK);
-
- assert((addr_ctrl & mask) == addr_ctrl);
- sampler->sampler[1] = (sampler->sampler[1] & ~mask) |
- addr_ctrl;
- }
-
- return true;
-}
-
-bool
-ilo_state_sampler_border_init(struct ilo_state_sampler_border *border,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_border_info *info)
-{
- bool ret = true;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- ret &= sampler_border_set_gen7_SAMPLER_BORDER_COLOR_STATE(border,
- dev, info);
- } else {
- ret &= sampler_border_set_gen6_SAMPLER_BORDER_COLOR_STATE(border,
- dev, info);
- }
-
- assert(ret);
-
- return ret;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_state_sampler.h b/src/gallium/drivers/ilo/core/ilo_state_sampler.h
deleted file mode 100644
index 75c7620a678..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_sampler.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_SAMPLER_H
-#define ILO_STATE_SAMPLER_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-struct ilo_state_surface;
-
-struct ilo_state_sampler_info {
- bool non_normalized;
-
- float lod_bias;
- float min_lod;
- float max_lod;
-
- enum gen_mip_filter mip_filter;
- enum gen_map_filter min_filter;
- enum gen_map_filter mag_filter;
- enum gen_aniso_ratio max_anisotropy;
-
- enum gen_texcoord_mode tcx_ctrl;
- enum gen_texcoord_mode tcy_ctrl;
- enum gen_texcoord_mode tcz_ctrl;
-
- enum gen_prefilter_op shadow_func;
-};
-
-struct ilo_state_sampler_border_info {
- union {
- float f[4];
- uint32_t ui[4];
- } rgba;
-
- bool is_integer;
-};
-
-struct ilo_state_sampler {
- uint32_t sampler[3];
-
- uint32_t filter_integer;
- uint32_t filter_3d;
-
- uint32_t addr_ctrl_1d;
- uint32_t addr_ctrl_2d_3d;
- uint32_t addr_ctrl_cube;
-
- bool non_normalized;
- bool base_to_surf_min_lod;
-};
-
-struct ilo_state_sampler_border {
- uint32_t color[12];
-};
-
-bool
-ilo_state_sampler_init(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_info *info);
-
-bool
-ilo_state_sampler_init_disabled(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev);
-
-bool
-ilo_state_sampler_set_surface(struct ilo_state_sampler *sampler,
- const struct ilo_dev *dev,
- const struct ilo_state_surface *surf);
-
-bool
-ilo_state_sampler_border_init(struct ilo_state_sampler_border *border,
- const struct ilo_dev *dev,
- const struct ilo_state_sampler_border_info *info);
-
-#endif /* ILO_STATE_SAMPLER_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_state_sbe.c b/src/gallium/drivers/ilo/core/ilo_state_sbe.c
deleted file mode 100644
index 1b4ca0683c9..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_sbe.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_sbe.h"
-
-static bool
-sbe_validate_gen8(const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(info->attr_count <= ILO_STATE_SBE_MAX_ATTR_COUNT);
-
- assert(info->vue_read_base + info->vue_read_count <=
- info->cv_vue_attr_count);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 248:
- *
- * "(Vertex URB Entry Read Length)
- * Format: U5
- * Range [1,16]
- *
- * Specifies the amount of URB data read for each Vertex URB entry, in
- * 256-bit register increments.
- *
- * Programming Notes
- * It is UNDEFINED to set this field to 0 indicating no Vertex URB
- * data to be read."
- *
- * "(Vertex URB Entry Read Offset)
- * Format: U6
- * Range [0,63]
- *
- * Specifies the offset (in 256-bit units) at which Vertex URB data is
- * to be read from the URB."
- */
- assert(info->vue_read_base % 2 == 0 && info->vue_read_base <= 126);
- assert(info->vue_read_count <= 32);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 268:
- *
- * "This field (Point Sprite Texture Coordinate Enable) must be
- * programmed to 0 when non-point primitives are rendered."
- */
- if (ilo_dev_gen(dev) < ILO_GEN(7.5) && info->point_sprite_enables)
- assert(info->cv_is_point);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 246:
- *
- * "(Number of SF Output Attributes) 33-48: Specifies 17-32 attributes
- * (# attributes = field value - 16). Swizzling performed on
- * Attributes 16-31 (as required) only. Attributes 0-15 passed through
- * unmodified.
- *
- * Note :
- *
- * Attribute n Component Override and Constant Source states apply to
- * Attributes 16-31 (as required) instead of Attributes 0-15. E.g.,
- * this allows an Attribute 16-31 component to be overridden with the
- * PrimitiveID value.
- *
- * Attribute n WrapShortest Enables still apply to Attributes 0-15.
- *
- * Attribute n Swizzle Select and Attribute n Source Attribute states
- * are ignored and none of the swizzling functions available through
- * these controls are performed."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 247:
- *
- * "This bit (Attribute Swizzle Enable) controls the use of the
- * Attribute n Swizzle Select and Attribute n Source Attribute fields
- * only. If ENABLED, those fields are used as described below. If
- * DISABLED, attributes are copied from their corresponding source
- * attributes, for the purposes of Swizzle Select only.
- *
- * Note that the following fields are unaffected by this bit, and are
- * therefore always used to control their respective fields:
- * Attribute n Component Override X/Y/Z/W
- * Attribute n Constant Source
- * Attribute n WrapShortest Enables"
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 264:
- *
- * "When Attribute Swizzle Enable is ENABLED, this bit (Attribute
- * Swizzle Control Mode) controls whether attributes 0-15 or 16-31 are
- * subject to the following swizzle controls:
- *
- * - Attribute n Component Override X/Y/Z/W
- * - Attribute n Constant Source
- * - Attribute n Swizzle Select
- * - Attribute n Source Attribute
- * - Attribute n Wrap Shortest Enables"
- *
- * "SWIZ_16_31... Only valid when 16 or more attributes are output."
- */
- assert(info->swizzle_count <= ILO_STATE_SBE_MAX_SWIZZLE_COUNT);
- if (info->swizzle_16_31) {
- assert(ilo_dev_gen(dev) >= ILO_GEN(7) &&
- info->swizzle_enable &&
- info->attr_count > 16);
- }
-
- return true;
-}
-
-static uint8_t
-sbe_get_gen8_min_read_count(const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- uint8_t min_count = 0;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* minimum read count for non-swizzled attributes */
- if (!info->swizzle_enable || info->swizzle_count < info->attr_count) {
- if (info->swizzle_16_31 && info->swizzle_count + 16 == info->attr_count)
- min_count = 16;
- else
- min_count = info->attr_count;
- }
-
- if (info->swizzle_enable) {
- uint8_t i;
-
- for (i = 0; i < info->swizzle_count; i++) {
- const struct ilo_state_sbe_swizzle_info *swizzle =
- &info->swizzles[i];
- bool inputattr_facing;
-
- switch (swizzle->attr_select) {
- case GEN6_INPUTATTR_FACING:
- case GEN6_INPUTATTR_FACING_W:
- inputattr_facing = true;
- break;
- default:
- inputattr_facing = false;
- break;
- }
-
- if (min_count < swizzle->attr + inputattr_facing + 1)
- min_count = swizzle->attr + inputattr_facing + 1;
- }
- }
-
- return min_count;
-}
-
-static uint8_t
-sbe_get_gen8_read_length(const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- uint8_t read_len;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 248:
- *
- * "(Vertex URB Entry Read Length)
- * This field should be set to the minimum length required to read the
- * maximum source attribute. The maximum source attribute is indicated
- * by the maximum value of the enabled Attribute # Source Attribute if
- * Attribute Swizzle Enable is set, Number of Output Attributes -1 if
- * enable is not set.
- * read_length = ceiling((max_source_attr+1)/2)
- *
- * [errata] Corruption/Hang possible if length programmed larger than
- * recommended"
- */
- if (info->has_min_read_count) {
- read_len = info->vue_read_count;
- assert(read_len == sbe_get_gen8_min_read_count(dev, info));
- } else {
- read_len = sbe_get_gen8_min_read_count(dev, info);
- assert(read_len <= info->vue_read_count);
- }
-
- /*
- * In pairs. URB entries are aligned to 1024-bits or 512-bits. There is
- * no need to worry about reading past entries.
- */
- read_len = (read_len + 1) / 2;
- if (!read_len)
- read_len = 1;
-
- return read_len;
-}
-
-static bool
-sbe_set_gen8_3DSTATE_SBE(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- uint8_t vue_read_offset, vue_read_len;
- uint8_t attr_count;
- uint32_t dw1, dw2, dw3;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!sbe_validate_gen8(dev, info))
- return false;
-
- vue_read_offset = info->vue_read_base / 2;
- vue_read_len = sbe_get_gen8_read_length(dev, info);
-
- attr_count = info->attr_count;
- if (ilo_dev_gen(dev) == ILO_GEN(6) && info->swizzle_16_31)
- attr_count += 16;
-
- dw1 = attr_count << GEN7_SBE_DW1_ATTR_COUNT__SHIFT |
- vue_read_len << GEN7_SBE_DW1_URB_READ_LEN__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- dw1 |= GEN8_SBE_DW1_FORCE_URB_READ_LEN |
- GEN8_SBE_DW1_FORCE_URB_READ_OFFSET |
- vue_read_offset << GEN8_SBE_DW1_URB_READ_OFFSET__SHIFT;
- } else {
- dw1 |= vue_read_offset << GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7) && info->swizzle_16_31)
- dw1 |= GEN7_SBE_DW1_ATTR_SWIZZLE_16_31;
-
- if (info->swizzle_enable)
- dw1 |= GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE;
-
- dw1 |= (info->point_sprite_origin_lower_left) ?
- GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT :
- GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT;
-
- dw2 = info->point_sprite_enables;
- dw3 = info->const_interp_enables;
-
- STATIC_ASSERT(ARRAY_SIZE(sbe->sbe) >= 3);
- sbe->sbe[0] = dw1;
- sbe->sbe[1] = dw2;
- sbe->sbe[2] = dw3;
-
- return true;
-}
-
-static bool
-sbe_set_gen8_3DSTATE_SBE_SWIZ(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- uint16_t swiz[ILO_STATE_SBE_MAX_SWIZZLE_COUNT];
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- for (i = 0; i < info->swizzle_count; i++) {
- const struct ilo_state_sbe_swizzle_info *swizzle = &info->swizzles[i];
-
- /* U5 */
- assert(swizzle->attr < 32);
- swiz[i] = swizzle->attr_select << GEN8_SBE_SWIZ_SWIZZLE_SELECT__SHIFT |
- swizzle->attr << GEN8_SBE_SWIZ_SRC_ATTR__SHIFT;
-
- if (swizzle->force_zeros) {
- swiz[i] |= GEN8_SBE_SWIZ_CONST_OVERRIDE_W |
- GEN8_SBE_SWIZ_CONST_OVERRIDE_Z |
- GEN8_SBE_SWIZ_CONST_OVERRIDE_Y |
- GEN8_SBE_SWIZ_CONST_OVERRIDE_X |
- GEN8_SBE_SWIZ_CONST_0000;
- }
- }
-
- for (; i < ARRAY_SIZE(swiz); i++) {
- swiz[i] = GEN6_INPUTATTR_NORMAL << GEN8_SBE_SWIZ_SWIZZLE_SELECT__SHIFT |
- i << GEN8_SBE_SWIZ_SRC_ATTR__SHIFT;
- }
-
- STATIC_ASSERT(sizeof(sbe->swiz) == sizeof(swiz));
- memcpy(sbe->swiz, swiz, sizeof(swiz));
-
- return true;
-}
-
-bool
-ilo_state_sbe_init(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- assert(ilo_is_zeroed(sbe, sizeof(*sbe)));
- return ilo_state_sbe_set_info(sbe, dev, info);
-}
-
-bool
-ilo_state_sbe_init_for_rectlist(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- uint8_t read_base,
- uint8_t read_count)
-{
- struct ilo_state_sbe_info info;
-
- memset(&info, 0, sizeof(info));
- info.attr_count = read_count;
- info.cv_vue_attr_count = read_base + read_count;
- info.vue_read_base = read_base;
- info.vue_read_count = read_count;
- info.has_min_read_count = true;
-
- return ilo_state_sbe_set_info(sbe, dev, &info);
-}
-
-bool
-ilo_state_sbe_set_info(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info)
-{
- bool ret = true;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- ret &= sbe_set_gen8_3DSTATE_SBE(sbe, dev, info);
- ret &= sbe_set_gen8_3DSTATE_SBE_SWIZ(sbe, dev, info);
-
- assert(ret);
-
- return true;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_state_sbe.h b/src/gallium/drivers/ilo/core/ilo_state_sbe.h
deleted file mode 100644
index 122999a9e94..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_sbe.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_SBE_H
-#define ILO_STATE_SBE_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Sandy Bridge PRM, volume 2 part 1, page 264:
- *
- * "Number of SF Output Attributes sets the number of attributes that will
- * be output from the SF stage, not including position. This can be used
- * to specify up to 32, and may differ from the number of input
- * attributes."
- *
- * "The first or last set of 16 attributes can be swizzled according to
- * certain state fields."
- */
-#define ILO_STATE_SBE_MAX_ATTR_COUNT 32
-#define ILO_STATE_SBE_MAX_SWIZZLE_COUNT 16
-
-struct ilo_state_sbe_swizzle_info {
- /* select an attribute from read ones */
- enum gen_inputattr_select attr_select;
- uint8_t attr;
-
- bool force_zeros;
-};
-
-struct ilo_state_sbe_info {
- uint8_t attr_count;
-
- /* which VUE attributes to read */
- uint8_t cv_vue_attr_count;
- uint8_t vue_read_base;
- uint8_t vue_read_count;
- bool has_min_read_count;
-
- bool cv_is_point;
- bool point_sprite_origin_lower_left;
- /* force sprite coordinates to the four corner vertices of the point */
- uint32_t point_sprite_enables;
-
- /* force attr at the provoking vertex to a0 and zero to a1/a2 */
- uint32_t const_interp_enables;
-
- bool swizzle_enable;
- /* swizzle attribute 16 to 31 instead; Gen7+ only */
- bool swizzle_16_31;
- uint8_t swizzle_count;
- const struct ilo_state_sbe_swizzle_info *swizzles;
-};
-
-struct ilo_state_sbe {
- uint32_t sbe[3];
- uint32_t swiz[8];
-};
-
-bool
-ilo_state_sbe_init(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info);
-
-bool
-ilo_state_sbe_init_for_rectlist(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- uint8_t read_base,
- uint8_t read_count);
-
-bool
-ilo_state_sbe_set_info(struct ilo_state_sbe *sbe,
- const struct ilo_dev *dev,
- const struct ilo_state_sbe_info *info);
-
-#endif /* ILO_STATE_SBE_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_state_shader.c b/src/gallium/drivers/ilo/core/ilo_state_shader.c
deleted file mode 100644
index aec4fd6d8a6..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_shader.c
+++ /dev/null
@@ -1,763 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_shader.h"
-
-enum vertex_stage {
- STAGE_VS,
- STAGE_HS,
- STAGE_DS,
- STAGE_GS,
-};
-
-struct vertex_ff {
- uint8_t grf_start;
-
- uint8_t per_thread_scratch_space;
- uint32_t per_thread_scratch_size;
-
- uint8_t sampler_count;
- uint8_t surface_count;
- bool has_uav;
-
- uint8_t vue_read_offset;
- uint8_t vue_read_len;
-
- uint8_t user_clip_enables;
-};
-
-static bool
-vertex_validate_gen6_kernel(const struct ilo_dev *dev,
- enum vertex_stage stage,
- const struct ilo_state_shader_kernel_info *kernel)
-{
- /*
- * "Dispatch GRF Start Register for URB Data" is U4 for GS and U5 for
- * others.
- */
- const uint8_t max_grf_start = (stage == STAGE_GS) ? 16 : 32;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* we do not want to save it */
- assert(!kernel->offset);
-
- assert(kernel->grf_start < max_grf_start);
-
- return true;
-}
-
-static bool
-vertex_validate_gen6_urb(const struct ilo_dev *dev,
- enum vertex_stage stage,
- const struct ilo_state_shader_urb_info *urb)
-{
- /* "Vertex/Patch URB Entry Read Offset" is U6, in pairs */
- const uint8_t max_read_base = 63 * 2;
- /*
- * "Vertex/Patch URB Entry Read Length" is limited to 64 for DS and U6 for
- * others, in pairs
- */
- const uint8_t max_read_count = ((stage == STAGE_DS) ? 64 : 63) * 2;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(urb->read_base + urb->read_count <= urb->cv_input_attr_count);
-
- assert(urb->read_base % 2 == 0 && urb->read_base <= max_read_base);
-
- /*
- * There is no need to worry about reading past entries, as URB entries are
- * aligned to 1024-bits (Gen6) or 512-bits (Gen7+).
- */
- assert(urb->read_count <= max_read_count);
-
- return true;
-}
-
-static bool
-vertex_get_gen6_ff(const struct ilo_dev *dev,
- enum vertex_stage stage,
- const struct ilo_state_shader_kernel_info *kernel,
- const struct ilo_state_shader_resource_info *resource,
- const struct ilo_state_shader_urb_info *urb,
- uint32_t per_thread_scratch_size,
- struct vertex_ff *ff)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- memset(ff, 0, sizeof(*ff));
-
- if (!vertex_validate_gen6_kernel(dev, stage, kernel) ||
- !vertex_validate_gen6_urb(dev, stage, urb))
- return false;
-
- ff->grf_start = kernel->grf_start;
-
- if (per_thread_scratch_size) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 134:
- *
- * "(Per-Thread Scratch Space)
- * Range [0,11] indicating [1K Bytes, 2M Bytes]"
- */
- assert(per_thread_scratch_size <= 2 * 1024 * 1024);
-
- /* next power of two, starting from 1KB */
- ff->per_thread_scratch_space = (per_thread_scratch_size > 1024) ?
- (util_last_bit(per_thread_scratch_size - 1) - 10) : 0;
- ff->per_thread_scratch_size = 1 << (10 + ff->per_thread_scratch_space);
- }
-
- ff->sampler_count = (resource->sampler_count <= 12) ?
- (resource->sampler_count + 3) / 4 : 4;
- ff->surface_count = resource->surface_count;
- ff->has_uav = resource->has_uav;
-
- ff->vue_read_offset = urb->read_base / 2;
- ff->vue_read_len = (urb->read_count + 1) / 2;
-
- /* need to read something unless VUE handles are included */
- switch (stage) {
- case STAGE_VS:
- if (!ff->vue_read_len)
- ff->vue_read_len = 1;
-
- /* one GRF per attribute */
- assert(kernel->grf_start + urb->read_count * 2 <= 128);
- break;
- case STAGE_GS:
- if (ilo_dev_gen(dev) == ILO_GEN(6) && !ff->vue_read_len)
- ff->vue_read_len = 1;
- break;
- default:
- break;
- }
-
- ff->user_clip_enables = urb->user_clip_enables;
-
- return true;
-}
-
-static uint16_t
-vs_get_gen6_thread_count(const struct ilo_dev *dev,
- const struct ilo_state_vs_info *info)
-{
- uint16_t thread_count;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* Maximum Number of Threads of 3DSTATE_VS */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- thread_count = 504;
- break;
- case ILO_GEN(7.5):
- thread_count = (dev->gt >= 2) ? 280 : 70;
- break;
- case ILO_GEN(7):
- case ILO_GEN(6):
- default:
- thread_count = dev->thread_count;
- break;
- }
-
- return thread_count - 1;
-}
-
-static bool
-vs_set_gen6_3DSTATE_VS(struct ilo_state_vs *vs,
- const struct ilo_dev *dev,
- const struct ilo_state_vs_info *info)
-{
- struct vertex_ff ff;
- uint16_t thread_count;
- uint32_t dw2, dw3, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!vertex_get_gen6_ff(dev, STAGE_VS, &info->kernel, &info->resource,
- &info->urb, info->per_thread_scratch_size, &ff))
- return false;
-
- thread_count = vs_get_gen6_thread_count(dev, info);
-
- dw2 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (false)
- dw2 |= GEN6_THREADDISP_FP_MODE_ALT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav)
- dw2 |= GEN75_THREADDISP_ACCESS_UAV;
-
- dw3 = ff.per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = ff.grf_start << GEN6_VS_DW4_URB_GRF_START__SHIFT |
- ff.vue_read_len << GEN6_VS_DW4_URB_READ_LEN__SHIFT |
- ff.vue_read_offset << GEN6_VS_DW4_URB_READ_OFFSET__SHIFT;
-
- dw5 = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- dw5 |= thread_count << GEN75_VS_DW5_MAX_THREADS__SHIFT;
- else
- dw5 |= thread_count << GEN6_VS_DW5_MAX_THREADS__SHIFT;
-
- if (info->stats_enable)
- dw5 |= GEN6_VS_DW5_STATISTICS;
- if (info->dispatch_enable)
- dw5 |= GEN6_VS_DW5_VS_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(vs->vs) >= 5);
- vs->vs[0] = dw2;
- vs->vs[1] = dw3;
- vs->vs[2] = dw4;
- vs->vs[3] = dw5;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- vs->vs[4] = ff.user_clip_enables << GEN8_VS_DW8_UCP_CLIP_ENABLES__SHIFT;
-
- vs->scratch_size = ff.per_thread_scratch_size * thread_count;
-
- return true;
-}
-
-static uint16_t
-hs_get_gen7_thread_count(const struct ilo_dev *dev,
- const struct ilo_state_hs_info *info)
-{
- uint16_t thread_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /* Maximum Number of Threads of 3DSTATE_HS */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- thread_count = 504;
- break;
- case ILO_GEN(7.5):
- thread_count = (dev->gt >= 2) ? 256 : 70;
- break;
- case ILO_GEN(7):
- default:
- thread_count = dev->thread_count;
- break;
- }
-
- return thread_count - 1;
-}
-
-static bool
-hs_set_gen7_3DSTATE_HS(struct ilo_state_hs *hs,
- const struct ilo_dev *dev,
- const struct ilo_state_hs_info *info)
-{
- struct vertex_ff ff;
- uint16_t thread_count;
- uint32_t dw1, dw2, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!vertex_get_gen6_ff(dev, STAGE_HS, &info->kernel, &info->resource,
- &info->urb, info->per_thread_scratch_size, &ff))
- return false;
-
- thread_count = hs_get_gen7_thread_count(dev, info);
-
- dw1 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- dw2 = 0 << GEN7_HS_DW2_INSTANCE_COUNT__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- dw2 |= thread_count << GEN8_HS_DW2_MAX_THREADS__SHIFT;
- else if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- dw1 |= thread_count << GEN75_HS_DW1_DISPATCH_MAX_THREADS__SHIFT;
- else
- dw1 |= thread_count << GEN7_HS_DW1_DISPATCH_MAX_THREADS__SHIFT;
-
- if (info->dispatch_enable)
- dw2 |= GEN7_HS_DW2_HS_ENABLE;
- if (info->stats_enable)
- dw2 |= GEN7_HS_DW2_STATISTICS;
-
- dw4 = ff.per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw5 = GEN7_HS_DW5_INCLUDE_VERTEX_HANDLES |
- ff.grf_start << GEN7_HS_DW5_URB_GRF_START__SHIFT |
- ff.vue_read_len << GEN7_HS_DW5_URB_READ_LEN__SHIFT |
- ff.vue_read_offset << GEN7_HS_DW5_URB_READ_OFFSET__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav)
- dw5 |= GEN75_HS_DW5_ACCESS_UAV;
-
- STATIC_ASSERT(ARRAY_SIZE(hs->hs) >= 4);
- hs->hs[0] = dw1;
- hs->hs[1] = dw2;
- hs->hs[2] = dw4;
- hs->hs[3] = dw5;
-
- hs->scratch_size = ff.per_thread_scratch_size * thread_count;
-
- return true;
-}
-
-static bool
-ds_set_gen7_3DSTATE_TE(struct ilo_state_ds *ds,
- const struct ilo_dev *dev,
- const struct ilo_state_ds_info *info)
-{
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- dw1 = 0;
-
- if (info->dispatch_enable) {
- dw1 |= GEN7_TE_DW1_MODE_HW |
- GEN7_TE_DW1_TE_ENABLE;
- }
-
- STATIC_ASSERT(ARRAY_SIZE(ds->te) >= 3);
- ds->te[0] = dw1;
- ds->te[1] = fui(63.0f);
- ds->te[2] = fui(64.0f);
-
- return true;
-}
-
-static uint16_t
-ds_get_gen7_thread_count(const struct ilo_dev *dev,
- const struct ilo_state_ds_info *info)
-{
- uint16_t thread_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /* Maximum Number of Threads of 3DSTATE_DS */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- thread_count = 504;
- break;
- case ILO_GEN(7.5):
- thread_count = (dev->gt >= 2) ? 280 : 70;
- break;
- case ILO_GEN(7):
- default:
- thread_count = dev->thread_count;
- break;
- }
-
- return thread_count - 1;
-}
-
-static bool
-ds_set_gen7_3DSTATE_DS(struct ilo_state_ds *ds,
- const struct ilo_dev *dev,
- const struct ilo_state_ds_info *info)
-{
- struct vertex_ff ff;
- uint16_t thread_count;
- uint32_t dw2, dw3, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!vertex_get_gen6_ff(dev, STAGE_DS, &info->kernel, &info->resource,
- &info->urb, info->per_thread_scratch_size, &ff))
- return false;
-
- thread_count = ds_get_gen7_thread_count(dev, info);
-
- dw2 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav)
- dw2 |= GEN75_THREADDISP_ACCESS_UAV;
-
- dw3 = ff.per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = ff.grf_start << GEN7_DS_DW4_URB_GRF_START__SHIFT |
- ff.vue_read_len << GEN7_DS_DW4_URB_READ_LEN__SHIFT |
- ff.vue_read_offset << GEN7_DS_DW4_URB_READ_OFFSET__SHIFT;
-
- dw5 = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- dw5 |= thread_count << GEN75_DS_DW5_MAX_THREADS__SHIFT;
- else
- dw5 |= thread_count << GEN7_DS_DW5_MAX_THREADS__SHIFT;
-
- if (info->stats_enable)
- dw5 |= GEN7_DS_DW5_STATISTICS;
- if (info->dispatch_enable)
- dw5 |= GEN7_DS_DW5_DS_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(ds->ds) >= 5);
- ds->ds[0] = dw2;
- ds->ds[1] = dw3;
- ds->ds[2] = dw4;
- ds->ds[3] = dw5;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- ds->ds[4] = ff.user_clip_enables << GEN8_DS_DW8_UCP_CLIP_ENABLES__SHIFT;
-
- ds->scratch_size = ff.per_thread_scratch_size * thread_count;
-
- return true;
-}
-
-static bool
-gs_get_gen6_ff(const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info,
- struct vertex_ff *ff)
-{
- const struct ilo_state_shader_urb_info *urb = &info->urb;
- const struct ilo_state_gs_sol_info *sol = &info->sol;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!vertex_get_gen6_ff(dev, STAGE_GS, &info->kernel, &info->resource,
- &info->urb, info->per_thread_scratch_size, ff))
- return false;
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 168-169:
- *
- * "[0,62] indicating [1,63] 16B units"
- *
- * "Programming Restrictions: The vertex size must be programmed as a
- * multiple of 32B units with the following exception: Rendering is
- * disabled (as per SOL stage state) and the vertex size output by the
- * GS thread is 16B.
- *
- * If rendering is enabled (as per SOL state) the vertex size must be
- * programmed as a multiple of 32B units. In other words, the only
- * time software can program a vertex size with an odd number of 16B
- * units is when rendering is disabled."
- */
- assert(urb->output_attr_count <= 63);
- if (!sol->render_disable)
- assert(urb->output_attr_count % 2 == 0);
-
- return true;
-}
-
-static uint16_t
-gs_get_gen6_thread_count(const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info)
-{
- const struct ilo_state_gs_sol_info *sol = &info->sol;
- uint16_t thread_count;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* Maximum Number of Threads of 3DSTATE_GS */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- thread_count = 504;
- break;
- case ILO_GEN(7.5):
- thread_count = (dev->gt >= 2) ? 256 : 70;
- break;
- case ILO_GEN(7):
- case ILO_GEN(6):
- default:
- thread_count = dev->thread_count;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 154:
- *
- * "Maximum Number of Threads valid range is [0,27] when Rendering
- * Enabled bit is set."
- *
- * According to the classic driver, [0, 20] for GT1.
- */
- if (!sol->render_disable)
- thread_count = (dev->gt == 2) ? 27 : 20;
- break;
- }
-
- return thread_count - 1;
-}
-
-static bool
-gs_set_gen6_3DSTATE_GS(struct ilo_state_gs *gs,
- const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info)
-{
- const struct ilo_state_gs_sol_info *sol = &info->sol;
- struct vertex_ff ff;
- uint16_t thread_count;
- uint32_t dw2, dw3, dw4, dw5, dw6;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- if (!gs_get_gen6_ff(dev, info, &ff))
- return false;
-
- thread_count = gs_get_gen6_thread_count(dev, info);
-
- dw2 = GEN6_THREADDISP_SPF |
- ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- dw3 = ff.per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = ff.vue_read_len << GEN6_GS_DW4_URB_READ_LEN__SHIFT |
- ff.vue_read_offset << GEN6_GS_DW4_URB_READ_OFFSET__SHIFT |
- ff.grf_start << GEN6_GS_DW4_URB_GRF_START__SHIFT;
-
- dw5 = thread_count << GEN6_GS_DW5_MAX_THREADS__SHIFT;
-
- if (info->stats_enable)
- dw5 |= GEN6_GS_DW5_STATISTICS;
- if (sol->stats_enable)
- dw5 |= GEN6_GS_DW5_SO_STATISTICS;
- if (!sol->render_disable)
- dw5 |= GEN6_GS_DW5_RENDER_ENABLE;
-
- dw6 = 0;
-
- /* GEN7_REORDER_TRAILING is handled by the kernel */
- if (sol->tristrip_reorder == GEN7_REORDER_LEADING)
- dw6 |= GEN6_GS_DW6_REORDER_LEADING_ENABLE;
-
- if (sol->sol_enable) {
- dw6 |= GEN6_GS_DW6_SVBI_PAYLOAD_ENABLE;
-
- if (sol->svbi_post_inc) {
- dw6 |= GEN6_GS_DW6_SVBI_POST_INC_ENABLE |
- sol->svbi_post_inc << GEN6_GS_DW6_SVBI_POST_INC_VAL__SHIFT;
- }
- }
-
- if (info->dispatch_enable)
- dw6 |= GEN6_GS_DW6_GS_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(gs->gs) >= 5);
- gs->gs[0] = dw2;
- gs->gs[1] = dw3;
- gs->gs[2] = dw4;
- gs->gs[3] = dw5;
- gs->gs[4] = dw6;
-
- gs->scratch_size = ff.per_thread_scratch_size * thread_count;
-
- return true;
-}
-
-static uint8_t
-gs_get_gen7_vertex_size(const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info)
-{
- const struct ilo_state_shader_urb_info *urb = &info->urb;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- return (urb->output_attr_count) ? urb->output_attr_count - 1 : 0;
-}
-
-static bool
-gs_set_gen7_3DSTATE_GS(struct ilo_state_gs *gs,
- const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info)
-{
- struct vertex_ff ff;
- uint16_t thread_count;
- uint8_t vertex_size;
- uint32_t dw2, dw3, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!gs_get_gen6_ff(dev, info, &ff))
- return false;
-
- thread_count = gs_get_gen6_thread_count(dev, info);
- vertex_size = gs_get_gen7_vertex_size(dev, info);
-
- dw2 = ff.sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff.surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff.has_uav)
- dw2 |= GEN75_THREADDISP_ACCESS_UAV;
-
- dw3 = ff.per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = vertex_size << GEN7_GS_DW4_OUTPUT_SIZE__SHIFT |
- 0 << GEN7_GS_DW4_OUTPUT_TOPO__SHIFT |
- ff.vue_read_len << GEN7_GS_DW4_URB_READ_LEN__SHIFT |
- GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES |
- ff.vue_read_offset << GEN7_GS_DW4_URB_READ_OFFSET__SHIFT |
- ff.grf_start << GEN7_GS_DW4_URB_GRF_START__SHIFT;
-
- dw5 = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- dw5 = thread_count << GEN75_GS_DW5_MAX_THREADS__SHIFT;
- else
- dw5 = thread_count << GEN7_GS_DW5_MAX_THREADS__SHIFT;
-
- if (info->stats_enable)
- dw5 |= GEN7_GS_DW5_STATISTICS;
- if (info->dispatch_enable)
- dw5 |= GEN7_GS_DW5_GS_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(gs->gs) >= 5);
- gs->gs[0] = dw2;
- gs->gs[1] = dw3;
- gs->gs[2] = dw4;
- gs->gs[3] = dw5;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- gs->gs[4] = ff.user_clip_enables << GEN8_GS_DW9_UCP_CLIP_ENABLES__SHIFT;
-
- gs->scratch_size = ff.per_thread_scratch_size * thread_count;
-
- return true;
-}
-
-bool
-ilo_state_vs_init(struct ilo_state_vs *vs,
- const struct ilo_dev *dev,
- const struct ilo_state_vs_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(vs, sizeof(*vs)));
-
- ret &= vs_set_gen6_3DSTATE_VS(vs, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_vs_init_disabled(struct ilo_state_vs *vs,
- const struct ilo_dev *dev)
-{
- struct ilo_state_vs_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_vs_init(vs, dev, &info);
-}
-
-bool
-ilo_state_hs_init(struct ilo_state_hs *hs,
- const struct ilo_dev *dev,
- const struct ilo_state_hs_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(hs, sizeof(*hs)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= hs_set_gen7_3DSTATE_HS(hs, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_hs_init_disabled(struct ilo_state_hs *hs,
- const struct ilo_dev *dev)
-{
- struct ilo_state_hs_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_hs_init(hs, dev, &info);
-}
-
-bool
-ilo_state_ds_init(struct ilo_state_ds *ds,
- const struct ilo_dev *dev,
- const struct ilo_state_ds_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(ds, sizeof(*ds)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- ret &= ds_set_gen7_3DSTATE_TE(ds, dev, info);
- ret &= ds_set_gen7_3DSTATE_DS(ds, dev, info);
- }
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_ds_init_disabled(struct ilo_state_ds *ds,
- const struct ilo_dev *dev)
-{
- struct ilo_state_ds_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_ds_init(ds, dev, &info);
-}
-
-bool
-ilo_state_gs_init(struct ilo_state_gs *gs,
- const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(gs, sizeof(*gs)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= gs_set_gen7_3DSTATE_GS(gs, dev, info);
- else
- ret &= gs_set_gen6_3DSTATE_GS(gs, dev, info);
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_gs_init_disabled(struct ilo_state_gs *gs,
- const struct ilo_dev *dev)
-{
- struct ilo_state_gs_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_gs_init(gs, dev, &info);
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_state_shader.h b/src/gallium/drivers/ilo/core/ilo_state_shader.h
deleted file mode 100644
index 35651090d66..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_shader.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_SHADER_H
-#define ILO_STATE_SHADER_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/**
- * Kernel information.
- */
-struct ilo_state_shader_kernel_info {
- /* usually 0 unless the shader has multiple kernels */
- uint32_t offset;
-
- uint8_t grf_start;
- uint8_t pcb_attr_count;
-};
-
-/**
- * Shader resources.
- */
-struct ilo_state_shader_resource_info {
- /* for prefetches */
- uint8_t sampler_count;
- uint8_t surface_count;
-
- bool has_uav;
-};
-
-/**
- * URB inputs/outputs.
- */
-struct ilo_state_shader_urb_info {
- uint8_t cv_input_attr_count;
-
- uint8_t read_base;
- uint8_t read_count;
-
- uint8_t output_attr_count;
-
- uint8_t user_cull_enables;
- uint8_t user_clip_enables;
-};
-
-struct ilo_state_vs_info {
- struct ilo_state_shader_kernel_info kernel;
- struct ilo_state_shader_resource_info resource;
- struct ilo_state_shader_urb_info urb;
-
- uint32_t per_thread_scratch_size;
- bool dispatch_enable;
- bool stats_enable;
-};
-
-struct ilo_state_hs_info {
- struct ilo_state_shader_kernel_info kernel;
- struct ilo_state_shader_resource_info resource;
- struct ilo_state_shader_urb_info urb;
-
- uint32_t per_thread_scratch_size;
- bool dispatch_enable;
- bool stats_enable;
-};
-
-struct ilo_state_ds_info {
- struct ilo_state_shader_kernel_info kernel;
- struct ilo_state_shader_resource_info resource;
- struct ilo_state_shader_urb_info urb;
-
- uint32_t per_thread_scratch_size;
- bool dispatch_enable;
- bool stats_enable;
-};
-
-/**
- * Stream output. Must be consistent with ilo_state_sol_info.
- */
-struct ilo_state_gs_sol_info {
- bool sol_enable;
- bool stats_enable;
- bool render_disable;
-
- uint16_t svbi_post_inc;
-
- enum gen_reorder_mode tristrip_reorder;
-};
-
-struct ilo_state_gs_info {
- struct ilo_state_shader_kernel_info kernel;
- struct ilo_state_shader_resource_info resource;
- struct ilo_state_shader_urb_info urb;
-
- struct ilo_state_gs_sol_info sol;
-
- uint32_t per_thread_scratch_size;
- bool dispatch_enable;
- bool stats_enable;
-};
-
-struct ilo_state_ps_io_info {
- /* inputs */
- enum gen_position_offset posoffset;
- uint8_t attr_count;
- bool use_z;
- bool use_w;
- bool use_coverage_mask;
-
- /* outputs */
- enum gen_pscdepth_mode pscdepth;
- bool has_rt_write;
- bool write_pixel_mask;
- bool write_omask;
-};
-
-struct ilo_state_ps_params_info {
- /* compatibility with raster states */
- uint32_t sample_mask;
- bool earlyz_control_psexec;
-
- /* compatibility with cc states */
- bool alpha_may_kill;
- bool dual_source_blending;
- bool has_writeable_rt;
-};
-
-struct ilo_state_ps_info {
- struct ilo_state_shader_kernel_info kernel_8;
- struct ilo_state_shader_kernel_info kernel_16;
- struct ilo_state_shader_kernel_info kernel_32;
- struct ilo_state_shader_resource_info resource;
-
- struct ilo_state_ps_io_info io;
- struct ilo_state_ps_params_info params;
-
- uint32_t per_thread_scratch_size;
-
- /* bitmask of GEN6_PS_DISPATCH_x */
- uint8_t valid_kernels;
- bool per_sample_dispatch;
- bool sample_count_one;
- bool cv_per_sample_interp;
- bool cv_has_earlyz_op;
-
- bool rt_clear_enable;
- bool rt_resolve_enable;
-
- bool cv_has_depth_buffer;
-};
-
-struct ilo_state_vs {
- uint32_t vs[5];
- uint32_t scratch_size;
-};
-
-struct ilo_state_hs {
- uint32_t hs[4];
- uint32_t scratch_size;
-};
-
-struct ilo_state_ds {
- uint32_t te[3];
- uint32_t ds[5];
- uint32_t scratch_size;
-};
-
-struct ilo_state_gs {
- uint32_t gs[5];
- uint32_t scratch_size;
-};
-
-struct ilo_state_ps {
- uint32_t ps[8];
- uint32_t scratch_size;
-
- struct ilo_state_ps_dispatch_conds {
- bool ps_valid;
-
- bool has_rt_write;
- bool write_odepth;
- bool write_ostencil;
- bool has_uav_write;
- bool ps_may_kill;
- } conds;
-};
-
-bool
-ilo_state_vs_init(struct ilo_state_vs *vs,
- const struct ilo_dev *dev,
- const struct ilo_state_vs_info *info);
-
-bool
-ilo_state_vs_init_disabled(struct ilo_state_vs *vs,
- const struct ilo_dev *dev);
-
-static inline uint32_t
-ilo_state_vs_get_scratch_size(const struct ilo_state_vs *vs)
-{
- return vs->scratch_size;
-}
-
-bool
-ilo_state_hs_init(struct ilo_state_hs *hs,
- const struct ilo_dev *dev,
- const struct ilo_state_hs_info *info);
-
-bool
-ilo_state_hs_init_disabled(struct ilo_state_hs *hs,
- const struct ilo_dev *dev);
-
-
-static inline uint32_t
-ilo_state_hs_get_scratch_size(const struct ilo_state_hs *hs)
-{
- return hs->scratch_size;
-}
-
-bool
-ilo_state_ds_init(struct ilo_state_ds *ds,
- const struct ilo_dev *dev,
- const struct ilo_state_ds_info *info);
-
-bool
-ilo_state_ds_init_disabled(struct ilo_state_ds *ds,
- const struct ilo_dev *dev);
-
-static inline uint32_t
-ilo_state_ds_get_scratch_size(const struct ilo_state_ds *ds)
-{
- return ds->scratch_size;
-}
-
-bool
-ilo_state_gs_init(struct ilo_state_gs *gs,
- const struct ilo_dev *dev,
- const struct ilo_state_gs_info *info);
-
-bool
-ilo_state_gs_init_disabled(struct ilo_state_gs *gs,
- const struct ilo_dev *dev);
-
-static inline uint32_t
-ilo_state_gs_get_scratch_size(const struct ilo_state_gs *gs)
-{
- return gs->scratch_size;
-}
-
-bool
-ilo_state_ps_init(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info);
-
-bool
-ilo_state_ps_init_disabled(struct ilo_state_ps *ps,
- const struct ilo_dev *dev);
-
-bool
-ilo_state_ps_set_params(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_params_info *params);
-
-static inline uint32_t
-ilo_state_ps_get_scratch_size(const struct ilo_state_ps *ps)
-{
- return ps->scratch_size;
-}
-
-#endif /* ILO_STATE_SHADER_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_state_shader_ps.c b/src/gallium/drivers/ilo/core/ilo_state_shader_ps.c
deleted file mode 100644
index 5c3ca1ebe37..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_shader_ps.c
+++ /dev/null
@@ -1,772 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_shader.h"
-
-struct pixel_ff {
- uint8_t dispatch_modes;
-
- uint32_t kernel_offsets[3];
- uint8_t grf_starts[3];
- bool pcb_enable;
- uint8_t per_thread_scratch_space;
- uint32_t per_thread_scratch_size;
-
- uint8_t sampler_count;
- uint8_t surface_count;
- bool has_uav;
-
- uint16_t thread_count;
-
- struct ilo_state_ps_dispatch_conds conds;
-
- bool kill_pixel;
- bool dispatch_enable;
- bool dual_source_blending;
- uint32_t sample_mask;
-};
-
-static bool
-ps_kernel_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_state_shader_kernel_info *kernel)
-{
- /* "Dispatch GRF Start Register for Constant/Setup Data" is U7 */
- const uint8_t max_grf_start = 128;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* "Kernel Start Pointer" is 64-byte aligned */
- assert(kernel->offset % 64 == 0);
-
- assert(kernel->grf_start < max_grf_start);
-
- return true;
-}
-
-static bool
-ps_validate_gen6(const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info)
-{
- const struct ilo_state_shader_kernel_info *kernel_8 = &info->kernel_8;
- const struct ilo_state_shader_kernel_info *kernel_16 = &info->kernel_16;
- const struct ilo_state_shader_kernel_info *kernel_32 = &info->kernel_32;
- const struct ilo_state_ps_io_info *io = &info->io;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!ps_kernel_validate_gen6(dev, kernel_8) ||
- !ps_kernel_validate_gen6(dev, kernel_16) ||
- !ps_kernel_validate_gen6(dev, kernel_32))
- return false;
-
- /* unsupported on Gen6 */
- if (ilo_dev_gen(dev) == ILO_GEN(6))
- assert(!io->use_coverage_mask);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 275:
- *
- * "If a NULL Depth Buffer is selected, the Pixel Shader Computed Depth
- * field must be set to disabled."
- */
- if (ilo_dev_gen(dev) == ILO_GEN(6) && io->pscdepth != GEN7_PSCDEPTH_OFF)
- assert(info->cv_has_depth_buffer);
-
- if (!info->per_sample_dispatch) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 281:
- *
- * "MSDISPMODE_PERSAMPLE is required in order to select
- * POSOFFSET_SAMPLE."
- */
- assert(io->posoffset != GEN6_POSOFFSET_SAMPLE);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 282:
- *
- * "MSDISPMODE_PERSAMPLE is required in order to select
- * INTERP_SAMPLE."
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 283:
- *
- * "MSDISPMODE_PERSAMPLE is required in order to select Perspective
- * Sample or Non-perspective Sample barycentric coordinates."
- */
- assert(!info->cv_per_sample_interp);
- }
-
- /*
- *
- * From the Sandy Bridge PRM, volume 2 part 1, page 314:
- *
- * "Pixel Shader Dispatch, Alpha... must all be disabled."
- *
- * Simply disallow any valid kernel when there is early-z op. Also, when
- * there is no valid kernel, io should be zeroed.
- */
- if (info->valid_kernels)
- assert(!info->cv_has_earlyz_op);
- else
- assert(ilo_is_zeroed(io, sizeof(*io)));
-
- return true;
-}
-
-static uint8_t
-ps_get_gen6_dispatch_modes(const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint8_t dispatch_modes = info->valid_kernels;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (!dispatch_modes)
- return 0;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 334:
- *
- * "Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
- * computed depth."
- *
- * "Valid on all products, except when in non-1x PERSAMPLE mode
- * (applies to [DevSNB+] only)"
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 239:
- *
- * "[DevSNB]: When Pixel Shader outputs oDepth and PS invocation mode
- * is PERPIXEL, Message Type for Render Target Write must be SIMD8.
- *
- * Errata: [DevSNB+]: When Pixel Shader outputs oMask, this message
- * type is not supported: SIMD8 (including SIMD8_DUALSRC_xx)."
- *
- * It is really hard to follow what combinations are valid on what
- * platforms. Judging from the restrictions on RT write messages on Gen6,
- * oDepth and oMask related issues should be Gen6-specific. PERSAMPLE
- * issue should be universal, and disallows multiple dispatch modes.
- */
- if (ilo_dev_gen(dev) == ILO_GEN(6)) {
- if (io->pscdepth != GEN7_PSCDEPTH_OFF && !info->per_sample_dispatch)
- dispatch_modes &= GEN6_PS_DISPATCH_8;
- if (io->write_omask)
- dispatch_modes &= ~GEN6_PS_DISPATCH_8;
- }
- if (info->per_sample_dispatch && !info->sample_count_one) {
- /* prefer 32 over 16 over 8 */
- if (dispatch_modes & GEN6_PS_DISPATCH_32)
- dispatch_modes &= GEN6_PS_DISPATCH_32;
- else if (dispatch_modes & GEN6_PS_DISPATCH_16)
- dispatch_modes &= GEN6_PS_DISPATCH_16;
- else
- dispatch_modes &= GEN6_PS_DISPATCH_8;
- }
-
- /*
- * From the Broadwell PRM, volume 2b, page 149:
- *
- * "When Render Target Fast Clear Enable is ENABLED or Render Target
- * Resolve Type = RESOLVE_PARTIAL or RESOLVE_FULL, this bit (8 Pixel
- * Dispatch or Dual-8 Pixel Dispatch Enable) must be DISABLED."
- */
- if (info->rt_clear_enable || info->rt_resolve_enable)
- dispatch_modes &= ~GEN6_PS_DISPATCH_8;
-
- assert(dispatch_modes);
-
- return dispatch_modes;
-}
-
-static uint16_t
-ps_get_gen6_thread_count(const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info)
-{
- uint16_t thread_count;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* Maximum Number of Threads of 3DSTATE_PS */
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- /* scaled automatically */
- thread_count = 64 - 1;
- break;
- case ILO_GEN(7.5):
- thread_count = (dev->gt == 3) ? 408 :
- (dev->gt == 2) ? 204 : 102;
- break;
- case ILO_GEN(7):
- thread_count = (dev->gt == 2) ? 172 : 48;
- break;
- case ILO_GEN(6):
- default:
- /* from the classic driver instead of the PRM */
- thread_count = (dev->gt == 2) ? 80 : 40;
- break;
- }
-
- return thread_count - 1;
-}
-
-static bool
-ps_params_get_gen6_kill_pixel(const struct ilo_dev *dev,
- const struct ilo_state_ps_params_info *params,
- const struct ilo_state_ps_dispatch_conds *conds)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 275:
- *
- * "This bit (Pixel Shader Kill Pixel), if ENABLED, indicates that the
- * PS kernel or color calculator has the ability to kill (discard)
- * pixels or samples, other than due to depth or stencil testing.
- * This bit is required to be ENABLED in the following situations:
- *
- * The API pixel shader program contains "killpix" or "discard"
- * instructions, or other code in the pixel shader kernel that can
- * cause the final pixel mask to differ from the pixel mask received
- * on dispatch.
- *
- * A sampler with chroma key enabled with kill pixel mode is used by
- * the pixel shader.
- *
- * Any render target has Alpha Test Enable or AlphaToCoverage Enable
- * enabled.
- *
- * The pixel shader kernel generates and outputs oMask.
- *
- * Note: As ClipDistance clipping is fully supported in hardware and
- * therefore not via PS instructions, there should be no need to
- * ENABLE this bit due to ClipDistance clipping."
- */
- return (conds->ps_may_kill || params->alpha_may_kill);
-}
-
-static bool
-ps_params_get_gen6_dispatch_enable(const struct ilo_dev *dev,
- const struct ilo_state_ps_params_info *params,
- const struct ilo_state_ps_dispatch_conds *conds)
-{
- /*
- * We want to skip dispatching when EarlyZ suffices. The conditions that
- * require dispatching are
- *
- * - PS writes RTs and RTs are writeable
- * - PS changes depth value and depth test/write is enabled
- * - PS changes stencil value and stencil test is enabled
- * - PS writes UAVs
- * - PS or CC kills pixels
- * - EDSC is PSEXEC, and depth test/write or stencil test is enabled
- */
- bool dispatch_required =
- ((conds->has_rt_write && params->has_writeable_rt) ||
- conds->write_odepth ||
- conds->write_ostencil ||
- conds->has_uav_write ||
- ps_params_get_gen6_kill_pixel(dev, params, conds) ||
- params->earlyz_control_psexec);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 280:
- *
- * "If EDSC_PSEXEC mode is selected, Thread Dispatch Enable must be
- * set."
- */
- if (ilo_dev_gen(dev) < ILO_GEN(8) && params->earlyz_control_psexec)
- dispatch_required = true;
-
- /* assert it is valid to dispatch */
- if (dispatch_required)
- assert(conds->ps_valid);
-
- return dispatch_required;
-}
-
-static bool
-ps_get_gen6_ff_kernels(const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- struct pixel_ff *ff)
-{
- const struct ilo_state_shader_kernel_info *kernel_8 = &info->kernel_8;
- const struct ilo_state_shader_kernel_info *kernel_16 = &info->kernel_16;
- const struct ilo_state_shader_kernel_info *kernel_32 = &info->kernel_32;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- ff->dispatch_modes = ps_get_gen6_dispatch_modes(dev, info);
-
- /* initialize kernel offsets and GRF starts */
- if (util_is_power_of_two(ff->dispatch_modes)) {
- if (ff->dispatch_modes & GEN6_PS_DISPATCH_8) {
- ff->kernel_offsets[0] = kernel_8->offset;
- ff->grf_starts[0] = kernel_8->grf_start;
- } else if (ff->dispatch_modes & GEN6_PS_DISPATCH_16) {
- ff->kernel_offsets[0] = kernel_16->offset;
- ff->grf_starts[0] = kernel_16->grf_start;
- } else if (ff->dispatch_modes & GEN6_PS_DISPATCH_32) {
- ff->kernel_offsets[0] = kernel_32->offset;
- ff->grf_starts[0] = kernel_32->grf_start;
- }
- } else {
- ff->kernel_offsets[0] = kernel_8->offset;
- ff->kernel_offsets[1] = kernel_32->offset;
- ff->kernel_offsets[2] = kernel_16->offset;
-
- ff->grf_starts[0] = kernel_8->grf_start;
- ff->grf_starts[1] = kernel_32->grf_start;
- ff->grf_starts[2] = kernel_16->grf_start;
- }
-
- /* we do not want to save it */
- assert(ff->kernel_offsets[0] == 0);
-
- ff->pcb_enable = (((ff->dispatch_modes & GEN6_PS_DISPATCH_8) &&
- kernel_8->pcb_attr_count) ||
- ((ff->dispatch_modes & GEN6_PS_DISPATCH_16) &&
- kernel_16->pcb_attr_count) ||
- ((ff->dispatch_modes & GEN6_PS_DISPATCH_32) &&
- kernel_32->pcb_attr_count));
-
- /* GPU hangs on Haswell if none of the dispatch mode bits is set */
- if (ilo_dev_gen(dev) == ILO_GEN(7.5) && !ff->dispatch_modes)
- ff->dispatch_modes |= GEN6_PS_DISPATCH_8;
-
- return true;
-}
-
-static bool
-ps_get_gen6_ff(const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- struct pixel_ff *ff)
-{
- const struct ilo_state_shader_resource_info *resource = &info->resource;
- const struct ilo_state_ps_io_info *io = &info->io;
- const struct ilo_state_ps_params_info *params = &info->params;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- memset(ff, 0, sizeof(*ff));
-
- if (!ps_validate_gen6(dev, info) || !ps_get_gen6_ff_kernels(dev, info, ff))
- return false;
-
- if (info->per_thread_scratch_size) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 271:
- *
- * "(Per-Thread Scratch Space)
- * Range [0,11] indicating [1k bytes, 2M bytes] in powers of two"
- */
- assert(info->per_thread_scratch_size <= 2 * 1024 * 1024);
-
- /* next power of two, starting from 1KB */
- ff->per_thread_scratch_space = (info->per_thread_scratch_size > 1024) ?
- (util_last_bit(info->per_thread_scratch_size - 1) - 10) : 0;
- ff->per_thread_scratch_size = 1 << (10 + ff->per_thread_scratch_space);
- }
-
- ff->sampler_count = (resource->sampler_count <= 12) ?
- (resource->sampler_count + 3) / 4 : 4;
- ff->surface_count = resource->surface_count;
- ff->has_uav = resource->has_uav;
-
- ff->thread_count = ps_get_gen6_thread_count(dev, info);
-
- ff->conds.ps_valid = (info->valid_kernels != 0x0);
- ff->conds.has_rt_write = io->has_rt_write;
- ff->conds.write_odepth = (io->pscdepth != GEN7_PSCDEPTH_OFF);
- ff->conds.write_ostencil = false;
- ff->conds.has_uav_write = resource->has_uav;
- ff->conds.ps_may_kill = (io->write_pixel_mask || io->write_omask);
-
- ff->kill_pixel = ps_params_get_gen6_kill_pixel(dev, params, &ff->conds);
- ff->dispatch_enable =
- ps_params_get_gen6_dispatch_enable(dev, params, &ff->conds);
- ff->dual_source_blending = params->dual_source_blending;
- ff->sample_mask = params->sample_mask;
-
- return true;
-}
-
-static bool
-ps_set_gen6_3dstate_wm(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- const struct pixel_ff *ff)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint32_t dw2, dw3, dw4, dw5, dw6;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- dw2 = ff->sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (false)
- dw2 |= GEN6_THREADDISP_FP_MODE_ALT;
-
- dw3 = ff->per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = ff->grf_starts[0] << GEN6_WM_DW4_URB_GRF_START0__SHIFT |
- ff->grf_starts[1] << GEN6_WM_DW4_URB_GRF_START1__SHIFT |
- ff->grf_starts[2] << GEN6_WM_DW4_URB_GRF_START2__SHIFT;
-
- dw5 = ff->thread_count << GEN6_WM_DW5_MAX_THREADS__SHIFT |
- ff->dispatch_modes << GEN6_WM_DW5_PS_DISPATCH_MODE__SHIFT;
-
- if (ff->kill_pixel)
- dw5 |= GEN6_WM_DW5_PS_KILL_PIXEL;
-
- if (io->pscdepth != GEN7_PSCDEPTH_OFF)
- dw5 |= GEN6_WM_DW5_PS_COMPUTE_DEPTH;
- if (io->use_z)
- dw5 |= GEN6_WM_DW5_PS_USE_DEPTH;
-
- if (ff->dispatch_enable)
- dw5 |= GEN6_WM_DW5_PS_DISPATCH_ENABLE;
-
- if (io->write_omask)
- dw5 |= GEN6_WM_DW5_PS_COMPUTE_OMASK;
- if (io->use_w)
- dw5 |= GEN6_WM_DW5_PS_USE_W;
-
- if (ff->dual_source_blending)
- dw5 |= GEN6_WM_DW5_PS_DUAL_SOURCE_BLEND;
-
- dw6 = io->attr_count << GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT |
- io->posoffset << GEN6_WM_DW6_PS_POSOFFSET__SHIFT;
-
- dw6 |= (info->per_sample_dispatch) ?
- GEN6_WM_DW6_MSDISPMODE_PERSAMPLE : GEN6_WM_DW6_MSDISPMODE_PERPIXEL;
-
- STATIC_ASSERT(ARRAY_SIZE(ps->ps) >= 7);
- ps->ps[0] = dw2;
- ps->ps[1] = dw3;
- ps->ps[2] = dw4;
- ps->ps[3] = dw5;
- ps->ps[4] = dw6;
- ps->ps[5] = ff->kernel_offsets[1];
- ps->ps[6] = ff->kernel_offsets[2];
-
- return true;
-}
-
-static bool
-ps_set_gen7_3dstate_wm(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- const struct pixel_ff *ff)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 7, 7.5);
-
- dw1 = io->pscdepth << GEN7_WM_DW1_PSCDEPTH__SHIFT;
-
- if (ff->dispatch_enable)
- dw1 |= GEN7_WM_DW1_PS_DISPATCH_ENABLE;
- if (ff->kill_pixel)
- dw1 |= GEN7_WM_DW1_PS_KILL_PIXEL;
-
- if (io->use_z)
- dw1 |= GEN7_WM_DW1_PS_USE_DEPTH;
- if (io->use_w)
- dw1 |= GEN7_WM_DW1_PS_USE_W;
- if (io->use_coverage_mask)
- dw1 |= GEN7_WM_DW1_PS_USE_COVERAGE_MASK;
-
- dw2 = (info->per_sample_dispatch) ?
- GEN7_WM_DW2_MSDISPMODE_PERSAMPLE : GEN7_WM_DW2_MSDISPMODE_PERPIXEL;
-
- STATIC_ASSERT(ARRAY_SIZE(ps->ps) >= 2);
- ps->ps[0] = dw1;
- ps->ps[1] = dw2;
-
- return true;
-}
-
-static bool
-ps_set_gen7_3DSTATE_PS(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- const struct pixel_ff *ff)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint32_t dw2, dw3, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 7, 7.5);
-
- dw2 = ff->sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (false)
- dw2 |= GEN6_THREADDISP_FP_MODE_ALT;
-
- dw3 = ff->per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw4 = io->posoffset << GEN7_PS_DW4_POSOFFSET__SHIFT |
- ff->dispatch_modes << GEN7_PS_DW4_DISPATCH_MODE__SHIFT;
-
- if (ilo_dev_gen(dev) == ILO_GEN(7.5)) {
- dw4 |= ff->thread_count << GEN75_PS_DW4_MAX_THREADS__SHIFT |
- (ff->sample_mask & 0xff) << GEN75_PS_DW4_SAMPLE_MASK__SHIFT;
- } else {
- dw4 |= ff->thread_count << GEN7_PS_DW4_MAX_THREADS__SHIFT;
- }
-
- if (ff->pcb_enable)
- dw4 |= GEN7_PS_DW4_PUSH_CONSTANT_ENABLE;
- if (io->attr_count)
- dw4 |= GEN7_PS_DW4_ATTR_ENABLE;
- if (io->write_omask)
- dw4 |= GEN7_PS_DW4_COMPUTE_OMASK;
- if (info->rt_clear_enable)
- dw4 |= GEN7_PS_DW4_RT_FAST_CLEAR;
- if (ff->dual_source_blending)
- dw4 |= GEN7_PS_DW4_DUAL_SOURCE_BLEND;
- if (info->rt_resolve_enable)
- dw4 |= GEN7_PS_DW4_RT_RESOLVE;
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5) && ff->has_uav)
- dw4 |= GEN75_PS_DW4_ACCESS_UAV;
-
- dw5 = ff->grf_starts[0] << GEN7_PS_DW5_URB_GRF_START0__SHIFT |
- ff->grf_starts[1] << GEN7_PS_DW5_URB_GRF_START1__SHIFT |
- ff->grf_starts[2] << GEN7_PS_DW5_URB_GRF_START2__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(ps->ps) >= 8);
- ps->ps[2] = dw2;
- ps->ps[3] = dw3;
- ps->ps[4] = dw4;
- ps->ps[5] = dw5;
- ps->ps[6] = ff->kernel_offsets[1];
- ps->ps[7] = ff->kernel_offsets[2];
-
- return true;
-}
-
-static bool
-ps_set_gen8_3DSTATE_PS(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- const struct pixel_ff *ff)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint32_t dw3, dw4, dw6, dw7;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- /*
- * Set VME here for correct computation of LODs and others. Not sure why
- * it is needed now.
- */
- dw3 = GEN6_THREADDISP_VME |
- ff->sampler_count << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
- ff->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
-
- if (false)
- dw3 |= GEN6_THREADDISP_FP_MODE_ALT;
-
- dw4 = ff->per_thread_scratch_space <<
- GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT;
-
- dw6 = ff->thread_count << GEN8_PS_DW6_MAX_THREADS__SHIFT |
- io->posoffset << GEN8_PS_DW6_POSOFFSET__SHIFT |
- ff->dispatch_modes << GEN8_PS_DW6_DISPATCH_MODE__SHIFT;
-
- if (ff->pcb_enable)
- dw6 |= GEN8_PS_DW6_PUSH_CONSTANT_ENABLE;
-
- if (info->rt_clear_enable)
- dw6 |= GEN8_PS_DW6_RT_FAST_CLEAR;
- if (info->rt_resolve_enable)
- dw6 |= GEN8_PS_DW6_RT_RESOLVE;
-
- dw7 = ff->grf_starts[0] << GEN8_PS_DW7_URB_GRF_START0__SHIFT |
- ff->grf_starts[1] << GEN8_PS_DW7_URB_GRF_START1__SHIFT |
- ff->grf_starts[2] << GEN8_PS_DW7_URB_GRF_START2__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(ps->ps) >= 6);
- ps->ps[0] = dw3;
- ps->ps[1] = dw4;
- ps->ps[2] = dw6;
- ps->ps[3] = dw7;
- ps->ps[4] = ff->kernel_offsets[1];
- ps->ps[5] = ff->kernel_offsets[2];
-
- return true;
-}
-
-static bool
-ps_set_gen8_3DSTATE_PS_EXTRA(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info,
- const struct pixel_ff *ff)
-{
- const struct ilo_state_ps_io_info *io = &info->io;
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- dw1 = io->pscdepth << GEN8_PSX_DW1_PSCDEPTH__SHIFT;
-
- if (info->valid_kernels)
- dw1 |= GEN8_PSX_DW1_VALID;
- if (!io->has_rt_write)
- dw1 |= GEN8_PSX_DW1_UAV_ONLY;
- if (io->write_omask)
- dw1 |= GEN8_PSX_DW1_COMPUTE_OMASK;
- if (io->write_pixel_mask)
- dw1 |= GEN8_PSX_DW1_KILL_PIXEL;
-
- if (io->use_z)
- dw1 |= GEN8_PSX_DW1_USE_DEPTH;
- if (io->use_w)
- dw1 |= GEN8_PSX_DW1_USE_W;
- if (io->attr_count)
- dw1 |= GEN8_PSX_DW1_ATTR_ENABLE;
-
- if (info->per_sample_dispatch)
- dw1 |= GEN8_PSX_DW1_PER_SAMPLE;
- if (ff->has_uav)
- dw1 |= GEN8_PSX_DW1_ACCESS_UAV;
- if (io->use_coverage_mask)
- dw1 |= GEN8_PSX_DW1_USE_COVERAGE_MASK;
-
- /*
- * From the Broadwell PRM, volume 2b, page 151:
- *
- * "When this bit (Pixel Shader Valid) clear the rest of this command
- * should also be clear.
- */
- if (!info->valid_kernels)
- dw1 = 0;
-
- STATIC_ASSERT(ARRAY_SIZE(ps->ps) >= 5);
- ps->ps[4] = dw1;
-
- return true;
-}
-
-bool
-ilo_state_ps_init(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_info *info)
-{
- struct pixel_ff ff;
- bool ret = true;
-
- assert(ilo_is_zeroed(ps, sizeof(*ps)));
-
- ret &= ps_get_gen6_ff(dev, info, &ff);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- ret &= ps_set_gen8_3DSTATE_PS(ps, dev, info, &ff);
- ret &= ps_set_gen8_3DSTATE_PS_EXTRA(ps, dev, info, &ff);
- } else if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- ret &= ps_set_gen7_3dstate_wm(ps, dev, info, &ff);
- ret &= ps_set_gen7_3DSTATE_PS(ps, dev, info, &ff);
- } else {
- ret &= ps_set_gen6_3dstate_wm(ps, dev, info, &ff);
- }
-
- ps->scratch_size = ff.per_thread_scratch_size * ff.thread_count;
- /* save conditions */
- ps->conds = ff.conds;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_ps_init_disabled(struct ilo_state_ps *ps,
- const struct ilo_dev *dev)
-{
- struct ilo_state_ps_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_ps_init(ps, dev, &info);
-}
-
-bool
-ilo_state_ps_set_params(struct ilo_state_ps *ps,
- const struct ilo_dev *dev,
- const struct ilo_state_ps_params_info *params)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /* modify sample mask */
- if (ilo_dev_gen(dev) == ILO_GEN(7.5)) {
- ps->ps[4] = (ps->ps[4] & ~GEN75_PS_DW4_SAMPLE_MASK__MASK) |
- (params->sample_mask & 0xff) << GEN75_PS_DW4_SAMPLE_MASK__SHIFT;
- }
-
- /* modify dispatch enable, pixel kill, and dual source blending */
- if (ilo_dev_gen(dev) < ILO_GEN(8)) {
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- if (ps_params_get_gen6_dispatch_enable(dev, params, &ps->conds))
- ps->ps[0] |= GEN7_WM_DW1_PS_DISPATCH_ENABLE;
- else
- ps->ps[0] &= ~GEN7_WM_DW1_PS_DISPATCH_ENABLE;
-
- if (ps_params_get_gen6_kill_pixel(dev, params, &ps->conds))
- ps->ps[0] |= GEN7_WM_DW1_PS_KILL_PIXEL;
- else
- ps->ps[0] &= ~GEN7_WM_DW1_PS_KILL_PIXEL;
-
- if (params->dual_source_blending)
- ps->ps[4] |= GEN7_PS_DW4_DUAL_SOURCE_BLEND;
- else
- ps->ps[4] &= ~GEN7_PS_DW4_DUAL_SOURCE_BLEND;
- } else {
- if (ps_params_get_gen6_dispatch_enable(dev, params, &ps->conds))
- ps->ps[3] |= GEN6_WM_DW5_PS_DISPATCH_ENABLE;
- else
- ps->ps[3] &= ~GEN6_WM_DW5_PS_DISPATCH_ENABLE;
-
- if (ps_params_get_gen6_kill_pixel(dev, params, &ps->conds))
- ps->ps[3] |= GEN6_WM_DW5_PS_KILL_PIXEL;
- else
- ps->ps[3] &= ~GEN6_WM_DW5_PS_KILL_PIXEL;
-
- if (params->dual_source_blending)
- ps->ps[3] |= GEN6_WM_DW5_PS_DUAL_SOURCE_BLEND;
- else
- ps->ps[3] &= ~GEN6_WM_DW5_PS_DUAL_SOURCE_BLEND;
- }
- }
-
- return true;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_state_sol.c b/src/gallium/drivers/ilo/core/ilo_state_sol.c
deleted file mode 100644
index 6ef2c91a592..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_sol.c
+++ /dev/null
@@ -1,467 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_vma.h"
-#include "ilo_state_sol.h"
-
-static bool
-sol_stream_validate_gen7(const struct ilo_dev *dev,
- const struct ilo_state_sol_stream_info *stream)
-{
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- assert(stream->vue_read_base + stream->vue_read_count <=
- stream->cv_vue_attr_count);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 200:
- *
- * "(Stream 0 Vertex Read Offset)
- * Format: U1 count of 256-bit units
- *
- * Specifies amount of data to skip over before reading back Stream 0
- * vertex data. Must be zero if the GS is enabled and the Output
- * Vertex Size field in 3DSTATE_GS is programmed to 0 (i.e., one 16B
- * unit)."
- *
- * "(Stream 0 Vertex Read Length)
- * Format: U5-1 count of 256-bit units
- *
- * Specifies amount of vertex data to read back for Stream 0 vertices,
- * starting at the Stream 0 Vertex Read Offset location. Maximum
- * readback is 17 256-bit units (34 128-bit vertex attributes). Read
- * data past the end of the valid vertex data has undefined contents,
- * and therefore shouldn't be used to source stream out data. Must be
- * zero (i.e., read length = 256b) if the GS is enabled and the Output
- * Vertex Size field in 3DSTATE_GS is programmed to 0 (i.e., one 16B
- * unit)."
- */
- assert(stream->vue_read_base == 0 || stream->vue_read_base == 2);
- assert(stream->vue_read_count <= 34);
-
- assert(stream->decl_count <= ILO_STATE_SOL_MAX_DECL_COUNT);
-
- for (i = 0; i < stream->decl_count; i++) {
- const struct ilo_state_sol_decl_info *decl = &stream->decls[i];
-
- assert(decl->is_hole || decl->attr < stream->vue_read_count);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 205:
- *
- * "There is only enough internal storage for the 128-bit vertex
- * header and 32 128-bit vertex attributes."
- */
- assert(decl->attr < 33);
-
- assert(decl->component_base < 4 &&
- decl->component_base + decl->component_count <= 4);
- assert(decl->buffer < ILO_STATE_SOL_MAX_BUFFER_COUNT);
- }
-
- return true;
-}
-
-static bool
-sol_validate_gen7(const struct ilo_dev *dev,
- const struct ilo_state_sol_info *info)
-{
- uint8_t i;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 198:
- *
- * "This bit (Render Stream Select) is used even if SO Function Enable
- * is DISABLED."
- *
- * From the Haswell PRM, volume 2b, page 796:
- *
- * "SO Function Enable must also be ENABLED in order for thiis field
- * (Render Stream Select) to select a stream for rendering. When SO
- * Function Enable is DISABLED and Rendering Disable is cleared (i.e.,
- * rendering is enabled), StreamID is ignored downstream of the SO
- * stage, allowing any stream to be rendered."
- *
- * We want Gen7 behavior, but we have to require users to follow Gen7.5
- * behavior: info->sol_enable must be set for info->render_stream to work.
- */
-
- for (i = 0; i < ARRAY_SIZE(info->streams); i++) {
- if (!sol_stream_validate_gen7(dev, &info->streams[i]))
- return false;
- }
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 208:
- *
- * "(Surface Pitch)
- * [0,2048] Must be 0 or a multiple of 4 Bytes."
- */
- for (i = 0; i < ARRAY_SIZE(info->buffer_strides); i++) {
- assert(info->buffer_strides[i] <= 2048 &&
- info->buffer_strides[i] % 4 == 0);
- }
-
- return true;
-}
-
-static bool
-sol_set_gen7_3DSTATE_STREAMOUT(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_info *info)
-{
- struct {
- uint8_t offset;
- uint8_t len;
- } vue_read[ILO_STATE_SOL_MAX_STREAM_COUNT];
- uint8_t i;
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!sol_validate_gen7(dev, info))
- return false;
-
- for (i = 0; i < ARRAY_SIZE(info->streams); i++) {
- const struct ilo_state_sol_stream_info *stream = &info->streams[i];
-
- vue_read[i].offset = stream->vue_read_base / 2;
- /*
- * In pairs minus 1. URB entries are aligned to 512-bits. There is no
- * need to worry about reading past entries.
- */
- vue_read[i].len = (stream->vue_read_count + 1) / 2;
- if (vue_read[i].len)
- vue_read[i].len--;
- }
-
- dw1 = info->render_stream << GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT |
- info->tristrip_reorder << GEN7_SO_DW1_REORDER_MODE__SHIFT;
-
- if (info->sol_enable)
- dw1 |= GEN7_SO_DW1_SO_ENABLE;
-
- if (info->render_disable)
- dw1 |= GEN7_SO_DW1_RENDER_DISABLE;
-
- if (info->stats_enable)
- dw1 |= GEN7_SO_DW1_STATISTICS;
-
- if (ilo_dev_gen(dev) < ILO_GEN(8)) {
- const uint8_t buffer_enables = ((bool) info->buffer_strides[3]) << 3 |
- ((bool) info->buffer_strides[2]) << 2 |
- ((bool) info->buffer_strides[1]) << 1 |
- ((bool) info->buffer_strides[0]);
- dw1 |= buffer_enables << GEN7_SO_DW1_BUFFER_ENABLES__SHIFT;
- }
-
- dw2 = vue_read[3].offset << GEN7_SO_DW2_STREAM3_READ_OFFSET__SHIFT |
- vue_read[3].len << GEN7_SO_DW2_STREAM3_READ_LEN__SHIFT |
- vue_read[2].offset << GEN7_SO_DW2_STREAM2_READ_OFFSET__SHIFT |
- vue_read[2].len << GEN7_SO_DW2_STREAM2_READ_LEN__SHIFT |
- vue_read[1].offset << GEN7_SO_DW2_STREAM1_READ_OFFSET__SHIFT |
- vue_read[1].len << GEN7_SO_DW2_STREAM1_READ_LEN__SHIFT |
- vue_read[0].offset << GEN7_SO_DW2_STREAM0_READ_OFFSET__SHIFT |
- vue_read[0].len << GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(sol->streamout) >= 2);
- sol->streamout[0] = dw1;
- sol->streamout[1] = dw2;
-
- memcpy(sol->strides, info->buffer_strides, sizeof(sol->strides));
-
- return true;
-}
-
-static bool
-sol_set_gen7_3DSTATE_SO_DECL_LIST(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_info *info,
- uint8_t max_decl_count)
-{
- uint64_t decl_list[ILO_STATE_SOL_MAX_DECL_COUNT];
- uint8_t decl_counts[ILO_STATE_SOL_MAX_STREAM_COUNT];
- uint8_t buffer_selects[ILO_STATE_SOL_MAX_STREAM_COUNT];
- uint32_t dw1, dw2;
- uint8_t i, j;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- memset(decl_list, 0, sizeof(decl_list[0]) * max_decl_count);
-
- for (i = 0; i < ARRAY_SIZE(info->streams); i++) {
- const struct ilo_state_sol_stream_info *stream = &info->streams[i];
-
- assert(stream->decl_count <= max_decl_count);
- decl_counts[i] = stream->decl_count;
- buffer_selects[i] = 0;
-
- for (j = 0; j < stream->decl_count; j++) {
- const struct ilo_state_sol_decl_info *decl = &stream->decls[j];
- const uint8_t mask = ((1 << decl->component_count) - 1) <<
- decl->component_base;
- uint16_t val;
-
- val = decl->buffer << GEN7_SO_DECL_OUTPUT_SLOT__SHIFT |
- mask << GEN7_SO_DECL_COMPONENT_MASK__SHIFT;
-
- if (decl->is_hole)
- val |= GEN7_SO_DECL_HOLE_FLAG;
- else
- val |= decl->attr << GEN7_SO_DECL_REG_INDEX__SHIFT;
-
- decl_list[j] |= (uint64_t) val << (16 * i);
- buffer_selects[i] |= 1 << decl->buffer;
- }
- }
-
- dw1 = buffer_selects[3] << GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__SHIFT |
- buffer_selects[2] << GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__SHIFT |
- buffer_selects[1] << GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__SHIFT |
- buffer_selects[0] << GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__SHIFT;
- dw2 = decl_counts[3] << GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__SHIFT |
- decl_counts[2] << GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__SHIFT |
- decl_counts[1] << GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__SHIFT |
- decl_counts[0] << GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(sol->so_decl) >= 2);
- sol->so_decl[0] = dw1;
- sol->so_decl[1] = dw2;
-
- STATIC_ASSERT(ARRAY_SIZE(sol->decl[0]) == 2);
- memcpy(sol->decl, decl_list, sizeof(sol->decl[0]) * max_decl_count);
- sol->decl_count = max_decl_count;
-
- return true;
-}
-
-static bool
-sol_buffer_validate_gen7(const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info)
-{
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 208:
- *
- * "(Surface Base Address) This field specifies the starting DWord
- * address..."
- */
- assert(info->offset % 4 == 0);
-
- if (info->vma) {
- assert(info->vma->vm_alignment % 4 == 0);
- assert(info->size && info->offset + info->size <= info->vma->vm_size);
- }
-
- /* Gen8+ only */
- if (info->write_offset_load || info->write_offset_save) {
- assert(ilo_dev_gen(dev) >= ILO_GEN(8) && info->write_offset_vma);
- assert(info->write_offset_offset + sizeof(uint32_t) <=
- info->write_offset_vma->vm_size);
- }
-
- /*
- * From the Broadwell PRM, volume 2b, page 206:
- *
- * "This field (Stream Offset) specifies the Offset in stream output
- * buffer to start at, or whether to append to the end of an existing
- * buffer. The Offset must be DWORD aligned."
- */
- if (info->write_offset_imm_enable) {
- assert(info->write_offset_load);
- assert(info->write_offset_imm % 4 == 0);
- }
-
- return true;
-}
-
-static uint32_t
-sol_buffer_get_gen6_size(const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 208:
- *
- * "(Surface End Address) This field specifies the ending DWord
- * address..."
- */
- return (info->vma) ? info->size & ~3 : 0;
-}
-
-static bool
-sol_buffer_set_gen7_3dstate_so_buffer(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info)
-{
- const uint32_t size = sol_buffer_get_gen6_size(dev, info);
-
- ILO_DEV_ASSERT(dev, 7, 7.5);
-
- if (!sol_buffer_validate_gen7(dev, info))
- return false;
-
- STATIC_ASSERT(ARRAY_SIZE(sb->so_buf) >= 2);
- sb->so_buf[0] = info->offset;
- sb->so_buf[1] = (size) ? info->offset + size : 0;
-
- return true;
-}
-
-static bool
-sol_buffer_set_gen8_3dstate_so_buffer(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info)
-{
- const uint32_t size = sol_buffer_get_gen6_size(dev, info);
- uint32_t dw1;
-
- ILO_DEV_ASSERT(dev, 8, 8);
-
- if (!sol_buffer_validate_gen7(dev, info))
- return false;
-
- dw1 = 0;
-
- if (info->vma)
- dw1 |= GEN8_SO_BUF_DW1_ENABLE;
- if (info->write_offset_load)
- dw1 |= GEN8_SO_BUF_DW1_OFFSET_WRITE_ENABLE;
- if (info->write_offset_save)
- dw1 |= GEN8_SO_BUF_DW1_OFFSET_ENABLE;
-
- STATIC_ASSERT(ARRAY_SIZE(sb->so_buf) >= 4);
- sb->so_buf[0] = dw1;
- sb->so_buf[1] = info->offset;
-
- /*
- * From the Broadwell PRM, volume 2b, page 205:
- *
- * "This field (Surface Size) specifies the size of buffer in number
- * DWords minus 1 of the buffer in Graphics Memory."
- */
- sb->so_buf[2] = (size) ? size / 4 - 1 : 0;
-
- /* load from imm or sb->write_offset_bo */
- sb->so_buf[3] = (info->write_offset_imm_enable) ?
- info->write_offset_imm : ~0u;
-
- return true;
-}
-
-bool
-ilo_state_sol_init(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(sol, sizeof(*sol)));
- assert(ilo_is_zeroed(info->data, info->data_size));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- uint8_t max_decl_count, i;
-
- max_decl_count = info->streams[0].decl_count;
- for (i = 1; i < ARRAY_SIZE(info->streams); i++) {
- if (max_decl_count < info->streams[i].decl_count)
- max_decl_count = info->streams[i].decl_count;
- }
-
- assert(ilo_state_sol_data_size(dev, max_decl_count) <= info->data_size);
- sol->decl = (uint32_t (*)[2]) info->data;
-
- ret &= sol_set_gen7_3DSTATE_STREAMOUT(sol, dev, info);
- ret &= sol_set_gen7_3DSTATE_SO_DECL_LIST(sol, dev, info, max_decl_count);
- }
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_sol_init_disabled(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- bool render_disable)
-{
- struct ilo_state_sol_info info;
-
- memset(&info, 0, sizeof(info));
- info.render_disable = render_disable;
-
- return ilo_state_sol_init(sol, dev, &info);
-}
-
-uint32_t
-ilo_state_sol_buffer_size(const struct ilo_dev *dev, uint32_t size,
- uint32_t *alignment)
-{
- /* DWord aligned without padding */
- *alignment = 4;
- return size;
-}
-
-bool
-ilo_state_sol_buffer_init(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(sb, sizeof(*sb)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- ret &= sol_buffer_set_gen8_3dstate_so_buffer(sb, dev, info);
- else
- ret &= sol_buffer_set_gen7_3dstate_so_buffer(sb, dev, info);
-
- sb->vma = info->vma;
- sb->write_offset_vma = info->write_offset_vma;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_sol_buffer_init_disabled(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev)
-{
- struct ilo_state_sol_buffer_info info;
-
- memset(&info, 0, sizeof(info));
-
- return ilo_state_sol_buffer_init(sb, dev, &info);
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_state_sol.h b/src/gallium/drivers/ilo/core/ilo_state_sol.h
deleted file mode 100644
index 92c5f94725b..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_sol.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_SOL_H
-#define ILO_STATE_SOL_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-/*
- * From the Ivy Bridge PRM, volume 2 part 1, page 193:
- *
- * "Incoming topologies are tagged with a 2-bit StreamID."
- */
-#define ILO_STATE_SOL_MAX_STREAM_COUNT 4
-
-/*
- * From the Ivy Bridge PRM, volume 2 part 1, page 195:
- *
- * "Up to four SO buffers are supported."
- */
-#define ILO_STATE_SOL_MAX_BUFFER_COUNT 4
-
-/*
- * From the Ivy Bridge PRM, volume 2 part 1, page 201:
- *
- * "All 128 decls..."
- */
-#define ILO_STATE_SOL_MAX_DECL_COUNT 128
-
-/**
- * Output a vertex attribute.
- */
-struct ilo_state_sol_decl_info {
- /* select an attribute from read ones */
- uint8_t attr;
- bool is_hole;
-
- /* which components to write */
- uint8_t component_base;
- uint8_t component_count;
-
- /* destination buffer */
- uint8_t buffer;
-};
-
-struct ilo_state_sol_stream_info {
- /* which VUE attributes to read */
- uint8_t cv_vue_attr_count;
- uint8_t vue_read_base;
- uint8_t vue_read_count;
-
- uint8_t decl_count;
- const struct ilo_state_sol_decl_info *decls;
-};
-
-struct ilo_state_sol_info {
- void *data;
- size_t data_size;
-
- bool sol_enable;
- bool stats_enable;
- enum gen_reorder_mode tristrip_reorder;
-
- bool render_disable;
- /* ignored when SOL is disabled */
- uint8_t render_stream;
-
- /* a buffer is disabled when its stride is zero */
- uint16_t buffer_strides[ILO_STATE_SOL_MAX_BUFFER_COUNT];
-
- struct ilo_state_sol_stream_info streams[ILO_STATE_SOL_MAX_STREAM_COUNT];
-};
-
-struct ilo_state_sol {
- uint32_t streamout[2];
- uint16_t strides[4];
-
- uint32_t so_decl[2];
- uint32_t (*decl)[2];
- uint8_t decl_count;
-};
-
-struct ilo_vma;
-
-struct ilo_state_sol_buffer_info {
- const struct ilo_vma *vma;
- uint32_t offset;
- uint32_t size;
-
- /* Gen8+ only; at least sizeof(uint32_t) bytes */
- const struct ilo_vma *write_offset_vma;
- uint32_t write_offset_offset;
-
- bool write_offset_load;
- bool write_offset_save;
-
- bool write_offset_imm_enable;
- uint32_t write_offset_imm;
-};
-
-struct ilo_state_sol_buffer {
- uint32_t so_buf[5];
-
- const struct ilo_vma *vma;
- const struct ilo_vma *write_offset_vma;
-};
-
-static inline size_t
-ilo_state_sol_data_size(const struct ilo_dev *dev, uint8_t max_decl_count)
-{
- const struct ilo_state_sol *so = NULL;
- return (ilo_dev_gen(dev) >= ILO_GEN(7)) ?
- sizeof(so->decl[0]) * max_decl_count : 0;
-}
-
-bool
-ilo_state_sol_init(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_info *info);
-
-bool
-ilo_state_sol_init_disabled(struct ilo_state_sol *sol,
- const struct ilo_dev *dev,
- bool render_disable);
-
-uint32_t
-ilo_state_sol_buffer_size(const struct ilo_dev *dev, uint32_t size,
- uint32_t *alignment);
-
-bool
-ilo_state_sol_buffer_init(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev,
- const struct ilo_state_sol_buffer_info *info);
-
-bool
-ilo_state_sol_buffer_init_disabled(struct ilo_state_sol_buffer *sb,
- const struct ilo_dev *dev);
-
-#endif /* ILO_STATE_SOL_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_state_surface.c b/src/gallium/drivers/ilo/core/ilo_state_surface.c
deleted file mode 100644
index 27c37535fc8..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_surface.c
+++ /dev/null
@@ -1,1270 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_image.h"
-#include "ilo_vma.h"
-#include "ilo_state_surface.h"
-
-static bool
-surface_set_gen6_null_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev)
-{
- uint32_t dw0, dw3;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 71:
- *
- * "All of the remaining fields in surface state are ignored for null
- * surfaces, with the following exceptions:
- *
- * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
- * depth buffer's corresponding state for all render target
- * surfaces, including null.
- * - Surface Format must be R8G8B8A8_UNORM."
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 82:
- *
- * "If Surface Type is SURFTYPE_NULL, this field (Tiled Surface) must
- * be true"
- *
- * Note that we ignore the first exception for all surface types.
- */
- dw0 = GEN6_SURFTYPE_NULL << GEN6_SURFACE_DW0_TYPE__SHIFT |
- GEN6_FORMAT_R8G8B8A8_UNORM << GEN6_SURFACE_DW0_FORMAT__SHIFT;
- dw3 = GEN6_TILING_X << GEN6_SURFACE_DW3_TILING__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 6);
- surf->surface[0] = dw0;
- surf->surface[1] = 0;
- surf->surface[2] = 0;
- surf->surface[3] = dw3;
- surf->surface[4] = 0;
- surf->surface[5] = 0;
-
- return true;
-}
-
-static bool
-surface_set_gen7_null_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev)
-{
- uint32_t dw0;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- dw0 = GEN6_SURFTYPE_NULL << GEN7_SURFACE_DW0_TYPE__SHIFT |
- GEN6_FORMAT_R8G8B8A8_UNORM << GEN7_SURFACE_DW0_FORMAT__SHIFT;
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- dw0 |= GEN6_TILING_X << GEN8_SURFACE_DW0_TILING__SHIFT;
- else
- dw0 |= GEN6_TILING_X << GEN7_SURFACE_DW0_TILING__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 13);
- surf->surface[0] = dw0;
- memset(&surf->surface[1], 0, sizeof(uint32_t) *
- (((ilo_dev_gen(dev) >= ILO_GEN(8)) ? 13 : 8) - 1));
-
- return true;
-}
-
-static uint32_t
-surface_get_gen6_buffer_offset_alignment(const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info)
-{
- uint32_t alignment;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 68:
- *
- * "The Base Address for linear render target surfaces and surfaces
- * accessed with the typed surface read/write data port messages must
- * be element-size aligned, for non-YUV surface formats, or a multiple
- * of 2 element-sizes for YUV surface formats. Other linear surfaces
- * have no alignment requirements (byte alignment is sufficient)."
- *
- * "Certain message types used to access surfaces have more stringent
- * alignment requirements. Please refer to the specific message
- * documentation for additional restrictions."
- */
- switch (info->access) {
- case ILO_STATE_SURFACE_ACCESS_SAMPLER:
- /* no alignment requirements */
- alignment = 1;
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
- case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
- /* element-size aligned */
- alignment = info->format_size;
-
- assert(info->struct_size % alignment == 0);
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_UNTYPED:
- /*
- * Nothing is said about Untyped* messages, but I think they require the
- * base address to be DWord aligned.
- */
- alignment = 4;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 70:
- *
- * "For linear surfaces with Surface Type of SURFTYPE_STRBUF, the
- * pitch must be a multiple of 4 bytes."
- */
- if (info->struct_size > 1)
- assert(info->struct_size % alignment == 0);
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_DATA:
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 233, 235, and 237:
- *
- * "the surface base address must be OWord aligned"
- *
- * for OWord Block Read/Write, Unaligned OWord Block Read, and OWord
- * Dual Block Read/Write.
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 246 and 249:
- *
- * "The surface base address must be DWord aligned"
- *
- * for DWord Scattered Read/Write and Byte Scattered Read/Write.
- */
- alignment = (info->format_size > 4) ? 16 : 4;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 233, 235, 237, and
- * 246:
- *
- * "the surface pitch is ignored, the surface is treated as a
- * 1-dimensional surface. An element size (pitch) of 16 bytes is
- * used to determine the size of the buffer for out-of-bounds
- * checking if using the surface state model."
- *
- * for OWord Block Read/Write, Unaligned OWord Block Read, OWord
- * Dual Block Read/Write, and DWord Scattered Read/Write.
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 248:
- *
- * "The surface pitch is ignored, the surface is treated as a
- * 1-dimensional surface. An element size (pitch) of 4 bytes is
- * used to determine the size of the buffer for out-of-bounds
- * checking if using the surface state model."
- *
- * for Byte Scattered Read/Write.
- *
- * It is programmable on Gen7.5+.
- */
- if (ilo_dev_gen(dev) < ILO_GEN(7.5)) {
- const int fixed = (info->format_size > 1) ? 16 : 4;
- assert(info->struct_size == fixed);
- }
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_SVB:
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 259:
- *
- * "Both the surface base address and surface pitch must be DWord
- * aligned."
- */
- alignment = 4;
-
- assert(info->struct_size % alignment == 0);
- break;
- default:
- assert(!"unknown access");
- alignment = 1;
- break;
- }
-
- return alignment;
-}
-
-static bool
-surface_validate_gen6_buffer(const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info)
-{
- uint32_t alignment;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->offset + info->size > info->vma->vm_size) {
- ilo_warn("invalid buffer range\n");
- return false;
- }
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 81:
- *
- * "For surfaces of type SURFTYPE_BUFFER: [0,2047] -> [1B, 2048B]
- * For surfaces of type SURFTYPE_STRBUF: [0,2047] -> [1B, 2048B]"
- */
- if (!info->struct_size || info->struct_size > 2048) {
- ilo_warn("invalid buffer struct size\n");
- return false;
- }
-
- alignment = surface_get_gen6_buffer_offset_alignment(dev, info);
- if (info->offset % alignment || info->vma->vm_alignment % alignment) {
- ilo_warn("bad buffer offset\n");
- return false;
- }
-
- /* no STRBUF on Gen6 */
- if (info->format == GEN6_FORMAT_RAW && info->struct_size > 1)
- assert(ilo_dev_gen(dev) >= ILO_GEN(7));
-
- /* SVB writes are Gen6 only */
- if (info->access == ILO_STATE_SURFACE_ACCESS_DP_SVB)
- assert(ilo_dev_gen(dev) == ILO_GEN(6));
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 83:
- *
- * "NOTE: "RAW" is supported only with buffers and structured buffers
- * accessed via the untyped surface read/write and untyped atomic
- * operation messages, which do not have a column in the table."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 252:
- *
- * "For untyped messages, the Surface Format must be RAW and the
- * Surface Type must be SURFTYPE_BUFFER or SURFTYPE_STRBUF."
- */
- assert((info->access == ILO_STATE_SURFACE_ACCESS_DP_UNTYPED) ==
- (info->format == GEN6_FORMAT_RAW));
-
- return true;
-}
-
-static bool
-surface_get_gen6_buffer_struct_count(const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info,
- uint32_t *count)
-{
- uint32_t max_struct, c;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- c = info->size / info->struct_size;
- if (info->format_size < info->size - info->struct_size * c)
- c++;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 77:
- *
- * "For buffer surfaces, the number of entries in the buffer ranges
- * from 1 to 2^27."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 68:
- *
- * "For typed buffer and structured buffer surfaces, the number of
- * entries in the buffer ranges from 1 to 2^27. For raw buffer
- * surfaces, the number of entries in the buffer is the number of
- * bytes which can range from 1 to 2^30."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 69:
- *
- * For SURFTYPE_BUFFER: The low two bits of this field (Width) must be
- * 11 if the Surface Format is RAW (the size of the buffer must be a
- * multiple of 4 bytes)."
- */
- max_struct = 1 << 27;
- if (info->format == GEN6_FORMAT_RAW && info->struct_size == 1) {
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- max_struct = 1 << 30;
-
- c &= ~3;
- }
-
- if (!c || c > max_struct) {
- ilo_warn("too many or zero buffer structs\n");
- return false;
- }
-
- *count = c - 1;
-
- return true;
-}
-
-static bool
-surface_set_gen6_buffer_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info)
-{
- uint32_t dw0, dw1, dw2, dw3;
- uint32_t struct_count;
- int width, height, depth;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- if (!surface_validate_gen6_buffer(dev, info) ||
- !surface_get_gen6_buffer_struct_count(dev, info, &struct_count))
- return false;
-
- /* bits [6:0] */
- width = (struct_count & 0x0000007f);
- /* bits [19:7] */
- height = (struct_count & 0x000fff80) >> 7;
- /* bits [26:20] */
- depth = (struct_count & 0x07f00000) >> 20;
-
- dw0 = GEN6_SURFTYPE_BUFFER << GEN6_SURFACE_DW0_TYPE__SHIFT |
- info->format << GEN6_SURFACE_DW0_FORMAT__SHIFT;
- dw1 = info->offset;
- dw2 = height << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
- width << GEN6_SURFACE_DW2_WIDTH__SHIFT;
- dw3 = depth << GEN6_SURFACE_DW3_DEPTH__SHIFT |
- (info->struct_size - 1) << GEN6_SURFACE_DW3_PITCH__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 6);
- surf->surface[0] = dw0;
- surf->surface[1] = dw1;
- surf->surface[2] = dw2;
- surf->surface[3] = dw3;
- surf->surface[4] = 0;
- surf->surface[5] = 0;
-
- surf->type = GEN6_SURFTYPE_BUFFER;
- surf->min_lod = 0;
- surf->mip_count = 0;
-
- return true;
-}
-
-static bool
-surface_set_gen7_buffer_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info)
-{
- uint32_t dw0, dw1, dw2, dw3, dw7;
- enum gen_surface_type type;
- uint32_t struct_count;
- int width, height, depth;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!surface_validate_gen6_buffer(dev, info) ||
- !surface_get_gen6_buffer_struct_count(dev, info, &struct_count))
- return false;
-
- type = (info->format == GEN6_FORMAT_RAW && info->struct_size > 1) ?
- GEN7_SURFTYPE_STRBUF : GEN6_SURFTYPE_BUFFER;
-
- /* bits [6:0] */
- width = (struct_count & 0x0000007f);
- /* bits [20:7] */
- height = (struct_count & 0x001fff80) >> 7;
- /* bits [30:21] */
- depth = (struct_count & 0x7fe00000) >> 21;
-
- dw0 = type << GEN7_SURFACE_DW0_TYPE__SHIFT |
- info->format << GEN7_SURFACE_DW0_FORMAT__SHIFT;
- dw1 = (ilo_dev_gen(dev) >= ILO_GEN(8)) ? 0 : info->offset;
- dw2 = GEN_SHIFT32(height, GEN7_SURFACE_DW2_HEIGHT) |
- GEN_SHIFT32(width, GEN7_SURFACE_DW2_WIDTH);
- dw3 = GEN_SHIFT32(depth, GEN7_SURFACE_DW3_DEPTH) |
- GEN_SHIFT32(info->struct_size - 1, GEN7_SURFACE_DW3_PITCH);
-
- dw7 = 0;
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- dw7 |= GEN_SHIFT32(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
- GEN_SHIFT32(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
- GEN_SHIFT32(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
- GEN_SHIFT32(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
- }
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 13);
- surf->surface[0] = dw0;
- surf->surface[1] = dw1;
- surf->surface[2] = dw2;
- surf->surface[3] = dw3;
- surf->surface[4] = 0;
- surf->surface[5] = 0;
- surf->surface[6] = 0;
- surf->surface[7] = dw7;
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- surf->surface[8] = info->offset;
- surf->surface[9] = 0;
- surf->surface[10] = 0;
- surf->surface[11] = 0;
- surf->surface[12] = 0;
- }
-
- surf->type = type;
- surf->min_lod = 0;
- surf->mip_count = 0;
-
- return true;
-}
-
-static bool
-surface_validate_gen6_image(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (info->access) {
- case ILO_STATE_SURFACE_ACCESS_SAMPLER:
- case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
- assert(ilo_dev_gen(dev) >= ILO_GEN(7));
- break;
- default:
- assert(!"unsupported surface access");
- break;
- }
-
- assert(info->img && info->vma);
-
- if (info->img->tiling != GEN6_TILING_NONE)
- assert(info->vma->vm_alignment % 4096 == 0);
-
- if (info->aux_vma) {
- assert(ilo_image_can_enable_aux(info->img, info->level_base));
- /* always tiled */
- assert(info->aux_vma->vm_alignment % 4096 == 0);
- }
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 78:
- *
- * "For surface types other than SURFTYPE_BUFFER, the Width specified
- * by this field must be less than or equal to the surface pitch
- * (specified in bytes via the Surface Pitch field)."
- */
- assert(info->img->bo_stride && info->img->bo_stride <= 512 * 1024 &&
- info->img->width0 <= info->img->bo_stride);
-
- if (info->type != info->img->type) {
- assert(info->type == GEN6_SURFTYPE_2D &&
- info->img->type == GEN6_SURFTYPE_CUBE);
- }
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 78:
- *
- * "For cube maps, Width must be set equal to the Height."
- */
- if (info->type == GEN6_SURFTYPE_CUBE)
- assert(info->img->width0 == info->img->height0);
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 72:
- *
- * "Tile Walk TILEWALK_YMAJOR is UNDEFINED for render target formats
- * that have 128 bits-per-element (BPE)."
- *
- * "If Number of Multisamples is set to a value other than
- * MULTISAMPLECOUNT_1, this field cannot be set to the following
- * formats:
- *
- * - any format with greater than 64 bits per element
- * - any compressed texture format (BC*)
- * - any YCRCB* format"
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 63:
- *
- * If Number of Multisamples is set to a value other than
- * MULTISAMPLECOUNT_1, this field cannot be set to the following
- * formats: any format with greater than 64 bits per element, if
- * Number of Multisamples is MULTISAMPLECOUNT_8, any compressed
- * texture format (BC*), and any YCRCB* format.
- *
- * TODO
- */
-
- if (ilo_dev_gen(dev) < ILO_GEN(8) && info->img->tiling == GEN8_TILING_W) {
- ilo_warn("tiling W is not supported\n");
- return false;
- }
-
- return true;
-}
-
-static void
-surface_get_gen6_image_max_extent(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- uint16_t *max_w, uint16_t *max_h)
-{
- const uint16_t max_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 16384 : 8192;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (info->type) {
- case GEN6_SURFTYPE_1D:
- *max_w = max_size;
- *max_h = 1;
- break;
- case GEN6_SURFTYPE_2D:
- case GEN6_SURFTYPE_CUBE:
- *max_w = max_size;
- *max_h = max_size;
- break;
- case GEN6_SURFTYPE_3D:
- *max_w = 2048;
- *max_h = 2048;
- break;
- default:
- assert(!"invalid surface type");
- *max_w = 1;
- *max_h = 1;
- break;
- }
-}
-
-static bool
-surface_get_gen6_image_extent(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- uint16_t *width, uint16_t *height)
-{
- uint16_t w, h, max_w, max_h;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- w = info->img->width0;
- h = info->img->height0;
-
- surface_get_gen6_image_max_extent(dev, info, &max_w, &max_h);
- assert(w && h && w <= max_w && h <= max_h);
-
- *width = w - 1;
- *height = h - 1;
-
- return true;
-}
-
-static bool
-surface_get_gen6_image_slices(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- uint16_t *depth, uint16_t *min_array_elem,
- uint16_t *rt_view_extent)
-{
- uint16_t max_slice, d;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 63:
- *
- * "If this field (Surface Array) is enabled, the Surface Type must be
- * SURFTYPE_1D, SURFTYPE_2D, or SURFTYPE_CUBE. If this field is
- * disabled and Surface Type is SURFTYPE_1D, SURFTYPE_2D, or
- * SURFTYPE_CUBE, the Depth field must be set to zero."
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 69:
- *
- * "This field (Depth) specifies the total number of levels for a
- * volume texture or the number of array elements allowed to be
- * accessed starting at the Minimum Array Element for arrayed
- * surfaces. If the volume texture is MIP-mapped, this field
- * specifies the depth of the base MIP level."
- *
- * "For SURFTYPE_CUBE:For Sampling Engine Surfaces, the range of this
- * field is [0,340], indicating the number of cube array elements
- * (equal to the number of underlying 2D array elements divided by 6).
- * For other surfaces, this field must be zero."
- *
- * "Errata: For SURFTYPE_CUBE sampling engine surfaces, the range of
- * this field is limited to [0,85].
- *
- * Errata: If Surface Array is enabled, and Depth is between 1024 and
- * 2047, an incorrect array slice may be accessed if the requested
- * array index in the message is greater than or equal to 4096."
- *
- * The errata are for Gen7-specific, and they limit the number of useable
- * layers to (86 * 6), about 512.
- */
-
- switch (info->type) {
- case GEN6_SURFTYPE_1D:
- case GEN6_SURFTYPE_2D:
- case GEN6_SURFTYPE_CUBE:
- max_slice = (ilo_dev_gen(dev) >= ILO_GEN(7.5)) ? 2048 : 512;
-
- assert(info->img->array_size <= max_slice);
- max_slice = info->img->array_size;
-
- d = info->slice_count;
- if (info->type == GEN6_SURFTYPE_CUBE) {
- if (info->access == ILO_STATE_SURFACE_ACCESS_SAMPLER) {
- if (!d || d % 6) {
- ilo_warn("invalid cube slice count\n");
- return false;
- }
-
- if (ilo_dev_gen(dev) == ILO_GEN(7) && d > 86 * 6) {
- ilo_warn("cube slice count exceeds Gen7 limit\n");
- return false;
- }
- } else {
- /*
- * Minumum Array Element and Depth must be 0; Render Target View
- * Extent is ignored.
- */
- if (info->slice_base || d != 6) {
- ilo_warn("no cube RT array support in data port\n");
- return false;
- }
- }
-
- d /= 6;
- }
-
- if (!info->is_array && d > 1) {
- ilo_warn("non-array surface with non-zero depth\n");
- return false;
- }
- break;
- case GEN6_SURFTYPE_3D:
- max_slice = 2048;
-
- assert(info->img->depth0 <= max_slice);
- max_slice = u_minify(info->img->depth0, info->level_base);
-
- d = info->img->depth0;
-
- if (info->is_array) {
- ilo_warn("3D surfaces cannot be arrays\n");
- return false;
- }
- break;
- default:
- assert(!"invalid surface type");
- return false;
- break;
- }
-
- if (!info->slice_count ||
- info->slice_base + info->slice_count > max_slice) {
- ilo_warn("invalid slice range\n");
- return false;
- }
-
- assert(d);
- *depth = d - 1;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 84:
- *
- * "For Sampling Engine and Render Target 1D and 2D Surfaces:
- * This field (Minimum Array Element) indicates the minimum array
- * element that can be accessed as part of this surface. This field
- * is added to the delivered array index before it is used to address
- * the surface.
- *
- * For Render Target 3D Surfaces:
- * This field indicates the minimum `R' coordinate on the LOD
- * currently being rendered to. This field is added to the delivered
- * array index before it is used to address the surface.
- *
- * For Sampling Engine Cube Surfaces on [DevSNB+] only:
- * This field indicates the minimum array element in the underlying 2D
- * surface array that can be accessed as part of this surface (the
- * cube array index is multipled by 6 to compute this value, although
- * this field is not restricted to only multiples of 6). This field is
- * added to the delivered array index before it is used to address the
- * surface.
- *
- * For Other Surfaces:
- * This field must be set to zero."
- *
- * On Gen7+, typed sufaces are treated like sampling engine 1D and 2D
- * surfaces.
- */
- *min_array_elem = info->slice_base;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 84:
- *
- * "For Render Target 3D Surfaces:
- * This field (Render Target View Extent) indicates the extent of the
- * accessible `R' coordinates minus 1 on the LOD currently being
- * rendered to.
- *
- * For Render Target 1D and 2D Surfaces:
- * This field must be set to the same value as the Depth field.
- *
- * For Other Surfaces:
- * This field is ignored."
- */
- *rt_view_extent = info->slice_count - 1;
-
- return true;
-}
-
-static bool
-surface_get_gen6_image_levels(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- uint8_t *min_lod, uint8_t *mip_count)
-{
- uint8_t max_level = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 15 : 14;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(info->img->level_count <= max_level);
- max_level = info->img->level_count;
-
- if (!info->level_count ||
- info->level_base + info->level_count > max_level) {
- ilo_warn("invalid level range\n");
- return false;
- }
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 79:
- *
- * "For Sampling Engine Surfaces:
- * This field (MIP Count / LOD) indicates the number of MIP levels
- * allowed to be accessed starting at Surface Min LOD, which must be
- * less than or equal to the number of MIP levels actually stored in
- * memory for this surface.
- *
- * Force the mip map access to be between the mipmap specified by the
- * integer bits of the Min LOD and the ceiling of the value specified
- * here.
- *
- * For Render Target Surfaces:
- * This field defines the MIP level that is currently being rendered
- * into. This is the absolute MIP level on the surface and is not
- * relative to the Surface Min LOD field, which is ignored for render
- * target surfaces.
- *
- * For Other Surfaces:
- * This field is reserved : MBZ"
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 83:
- *
- * "For Sampling Engine Surfaces:
- *
- * This field (Surface Min LOD) indicates the most detailed LOD that
- * can be accessed as part of this surface. This field is added to
- * the delivered LOD (sample_l, ld, or resinfo message types) before
- * it is used to address the surface.
- *
- * For Other Surfaces:
- * This field is ignored."
- *
- * On Gen7+, typed sufaces are treated like sampling engine surfaces.
- */
- if (info->access == ILO_STATE_SURFACE_ACCESS_DP_RENDER) {
- assert(info->level_count == 1);
-
- *min_lod = 0;
- *mip_count = info->level_base;
- } else {
- *min_lod = info->level_base;
- *mip_count = info->level_count - 1;
- }
-
- return true;
-}
-
-static bool
-surface_get_gen6_image_sample_count(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- enum gen_sample_count *sample_count)
-{
- int min_gen;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- switch (info->img->sample_count) {
- case 1:
- *sample_count = GEN6_NUMSAMPLES_1;
- min_gen = ILO_GEN(6);
- break;
- case 2:
- *sample_count = GEN8_NUMSAMPLES_2;
- min_gen = ILO_GEN(8);
- break;
- case 4:
- *sample_count = GEN6_NUMSAMPLES_4;
- min_gen = ILO_GEN(6);
- break;
- case 8:
- *sample_count = GEN7_NUMSAMPLES_8;
- min_gen = ILO_GEN(7);
- break;
- default:
- assert(!"invalid sample count");
- *sample_count = GEN6_NUMSAMPLES_1;
- break;
- }
-
- assert(ilo_dev_gen(dev) >= min_gen);
-
- return true;
-}
-
-static bool
-surface_get_gen6_image_alignments(const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info,
- uint32_t *alignments)
-{
- uint32_t a = 0;
- bool err = false;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- switch (info->img->align_i) {
- case 4:
- a |= GEN8_SURFACE_DW0_HALIGN_4;
- break;
- case 8:
- a |= GEN8_SURFACE_DW0_HALIGN_8;
- break;
- case 16:
- a |= GEN8_SURFACE_DW0_HALIGN_16;
- break;
- default:
- err = true;
- break;
- }
-
- switch (info->img->align_j) {
- case 4:
- a |= GEN7_SURFACE_DW0_VALIGN_4;
- break;
- case 8:
- a |= GEN8_SURFACE_DW0_VALIGN_8;
- break;
- case 16:
- a |= GEN8_SURFACE_DW0_VALIGN_16;
- break;
- default:
- err = true;
- break;
- }
- } else if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- switch (info->img->align_i) {
- case 4:
- a |= GEN7_SURFACE_DW0_HALIGN_4;
- break;
- case 8:
- a |= GEN7_SURFACE_DW0_HALIGN_8;
- break;
- default:
- err = true;
- break;
- }
-
- switch (info->img->align_j) {
- case 2:
- a |= GEN7_SURFACE_DW0_VALIGN_2;
- break;
- case 4:
- a |= GEN7_SURFACE_DW0_VALIGN_4;
- break;
- default:
- err = true;
- break;
- }
- } else {
- if (info->img->align_i != 4)
- err = true;
-
- switch (info->img->align_j) {
- case 2:
- a |= GEN6_SURFACE_DW5_VALIGN_2;
- break;
- case 4:
- a |= GEN6_SURFACE_DW5_VALIGN_4;
- break;
- default:
- err = true;
- break;
- }
- }
-
- if (err)
- assert(!"invalid HALIGN or VALIGN");
-
- *alignments = a;
-
- return true;
-}
-
-static bool
-surface_set_gen6_image_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info)
-{
- uint16_t width, height, depth, array_base, view_extent;
- uint8_t min_lod, mip_count;
- enum gen_sample_count sample_count;
- uint32_t alignments;
- uint32_t dw0, dw2, dw3, dw4, dw5;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- if (!surface_validate_gen6_image(dev, info) ||
- !surface_get_gen6_image_extent(dev, info, &width, &height) ||
- !surface_get_gen6_image_slices(dev, info, &depth, &array_base,
- &view_extent) ||
- !surface_get_gen6_image_levels(dev, info, &min_lod, &mip_count) ||
- !surface_get_gen6_image_sample_count(dev, info, &sample_count) ||
- !surface_get_gen6_image_alignments(dev, info, &alignments))
- return false;
-
- /* no ARYSPC_LOD0 */
- assert(info->img->walk != ILO_IMAGE_WALK_LOD);
- /* no UMS/CMS */
- if (info->img->sample_count > 1)
- assert(info->img->interleaved_samples);
-
- dw0 = info->type << GEN6_SURFACE_DW0_TYPE__SHIFT |
- info->format << GEN6_SURFACE_DW0_FORMAT__SHIFT |
- GEN6_SURFACE_DW0_MIPLAYOUT_BELOW;
-
- /*
- * From the Sandy Bridge PRM, volume 4 part 1, page 74:
- *
- * "CUBE_AVERAGE may only be selected if all of the Cube Face Enable
- * fields are equal to one."
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 75-76:
- *
- * "For SURFTYPE_CUBE Surfaces accessed via the Sampling Engine:
- * Bits 5:0 of this field (Cube Face Enables) enable the individual
- * faces of a cube map. Enabling a face indicates that the face is
- * present in the cube map, while disabling it indicates that that
- * face is represented by the texture map's border color. Refer to
- * Memory Data Formats for the correlation between faces and the cube
- * map memory layout. Note that storage for disabled faces must be
- * provided.
- *
- * For other surfaces:
- * This field is reserved : MBZ"
- *
- * "When TEXCOORDMODE_CLAMP is used when accessing a cube map, this
- * field must be programmed to 111111b (all faces enabled)."
- */
- if (info->type == GEN6_SURFTYPE_CUBE &&
- info->access == ILO_STATE_SURFACE_ACCESS_SAMPLER) {
- dw0 |= GEN6_SURFACE_DW0_CUBE_MAP_CORNER_MODE_AVERAGE |
- GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
- }
-
- dw2 = height << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
- width << GEN6_SURFACE_DW2_WIDTH__SHIFT |
- mip_count << GEN6_SURFACE_DW2_MIP_COUNT_LOD__SHIFT;
-
- dw3 = depth << GEN6_SURFACE_DW3_DEPTH__SHIFT |
- (info->img->bo_stride - 1) << GEN6_SURFACE_DW3_PITCH__SHIFT |
- info->img->tiling << GEN6_SURFACE_DW3_TILING__SHIFT;
-
- dw4 = min_lod << GEN6_SURFACE_DW4_MIN_LOD__SHIFT |
- array_base << GEN6_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT |
- view_extent << GEN6_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT |
- sample_count << GEN6_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT;
-
- dw5 = alignments;
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 6);
- surf->surface[0] = dw0;
- surf->surface[1] = 0;
- surf->surface[2] = dw2;
- surf->surface[3] = dw3;
- surf->surface[4] = dw4;
- surf->surface[5] = dw5;
-
- surf->type = info->type;
- surf->min_lod = min_lod;
- surf->mip_count = mip_count;
-
- return true;
-}
-
-static bool
-surface_set_gen7_image_SURFACE_STATE(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info)
-{
- uint16_t width, height, depth, array_base, view_extent;
- uint8_t min_lod, mip_count;
- uint32_t alignments;
- enum gen_sample_count sample_count;
- uint32_t dw0, dw1, dw2, dw3, dw4, dw5, dw7;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- if (!surface_validate_gen6_image(dev, info) ||
- !surface_get_gen6_image_extent(dev, info, &width, &height) ||
- !surface_get_gen6_image_slices(dev, info, &depth, &array_base,
- &view_extent) ||
- !surface_get_gen6_image_levels(dev, info, &min_lod, &mip_count) ||
- !surface_get_gen6_image_sample_count(dev, info, &sample_count) ||
- !surface_get_gen6_image_alignments(dev, info, &alignments))
- return false;
-
- dw0 = info->type << GEN7_SURFACE_DW0_TYPE__SHIFT |
- info->format << GEN7_SURFACE_DW0_FORMAT__SHIFT |
- alignments;
-
- if (info->is_array)
- dw0 |= GEN7_SURFACE_DW0_IS_ARRAY;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- dw0 |= info->img->tiling << GEN8_SURFACE_DW0_TILING__SHIFT;
- } else {
- dw0 |= info->img->tiling << GEN7_SURFACE_DW0_TILING__SHIFT;
-
- if (info->img->walk == ILO_IMAGE_WALK_LOD)
- dw0 |= GEN7_SURFACE_DW0_ARYSPC_LOD0;
- else
- dw0 |= GEN7_SURFACE_DW0_ARYSPC_FULL;
- }
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 67:
- *
- * "For SURFTYPE_CUBE Surfaces accessed via the Sampling Engine: Bits
- * 5:0 of this field (Cube Face Enables) enable the individual faces
- * of a cube map. Enabling a face indicates that the face is present
- * in the cube map, while disabling it indicates that that face is
- * represented by the texture map's border color. Refer to Memory Data
- * Formats for the correlation between faces and the cube map memory
- * layout. Note that storage for disabled faces must be provided. For
- * other surfaces this field is reserved and MBZ."
- *
- * "When TEXCOORDMODE_CLAMP is used when accessing a cube map, this
- * field must be programmed to 111111b (all faces enabled). This field
- * is ignored unless the Surface Type is SURFTYPE_CUBE."
- */
- if (info->type == GEN6_SURFTYPE_CUBE &&
- info->access == ILO_STATE_SURFACE_ACCESS_SAMPLER)
- dw0 |= GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
-
- dw1 = 0;
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- assert(info->img->walk_layer_height % 4 == 0);
- dw1 |= info->img->walk_layer_height / 4 <<
- GEN8_SURFACE_DW1_QPITCH__SHIFT;
- }
-
- dw2 = height << GEN7_SURFACE_DW2_HEIGHT__SHIFT |
- width << GEN7_SURFACE_DW2_WIDTH__SHIFT;
-
- dw3 = depth << GEN7_SURFACE_DW3_DEPTH__SHIFT |
- (info->img->bo_stride - 1) << GEN7_SURFACE_DW3_PITCH__SHIFT;
-
- if (ilo_dev_gen(dev) == ILO_GEN(7.5))
- dw3 |= 0 << GEN75_SURFACE_DW3_INTEGER_SURFACE_FORMAT__SHIFT;
-
- dw4 = array_base << GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT__SHIFT |
- view_extent << GEN7_SURFACE_DW4_RT_VIEW_EXTENT__SHIFT |
- sample_count << GEN7_SURFACE_DW4_MULTISAMPLECOUNT__SHIFT;
-
- /*
- * MSFMT_MSS means the samples are not interleaved and MSFMT_DEPTH_STENCIL
- * means the samples are interleaved. The layouts are the same when the
- * number of samples is 1.
- */
- if (info->img->interleaved_samples && info->img->sample_count > 1) {
- assert(info->access != ILO_STATE_SURFACE_ACCESS_DP_RENDER);
- dw4 |= GEN7_SURFACE_DW4_MSFMT_DEPTH_STENCIL;
- } else {
- dw4 |= GEN7_SURFACE_DW4_MSFMT_MSS;
- }
-
- dw5 = min_lod << GEN7_SURFACE_DW5_MIN_LOD__SHIFT |
- mip_count << GEN7_SURFACE_DW5_MIP_COUNT_LOD__SHIFT;
-
- dw7 = 0;
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5)) {
- dw7 |= GEN_SHIFT32(GEN75_SCS_RED, GEN75_SURFACE_DW7_SCS_R) |
- GEN_SHIFT32(GEN75_SCS_GREEN, GEN75_SURFACE_DW7_SCS_G) |
- GEN_SHIFT32(GEN75_SCS_BLUE, GEN75_SURFACE_DW7_SCS_B) |
- GEN_SHIFT32(GEN75_SCS_ALPHA, GEN75_SURFACE_DW7_SCS_A);
- }
-
- STATIC_ASSERT(ARRAY_SIZE(surf->surface) >= 13);
- surf->surface[0] = dw0;
- surf->surface[1] = dw1;
- surf->surface[2] = dw2;
- surf->surface[3] = dw3;
- surf->surface[4] = dw4;
- surf->surface[5] = dw5;
- surf->surface[6] = 0;
- surf->surface[7] = dw7;
- if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
- surf->surface[8] = 0;
- surf->surface[9] = 0;
- surf->surface[10] = 0;
- surf->surface[11] = 0;
- surf->surface[12] = 0;
- }
-
- surf->type = info->type;
- surf->min_lod = min_lod;
- surf->mip_count = mip_count;
-
- return true;
-}
-
-uint32_t
-ilo_state_surface_buffer_size(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- uint32_t size, uint32_t *alignment)
-{
- switch (access) {
- case ILO_STATE_SURFACE_ACCESS_SAMPLER:
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 118:
- *
- * "For buffers, which have no inherent "height," padding
- * requirements are different. A buffer must be padded to the next
- * multiple of 256 array elements, with an additional 16 bytes
- * added beyond that to account for the L1 cache line."
- *
- * Assuming tightly packed GEN6_FORMAT_R32G32B32A32_FLOAT, the size
- * needs to be padded to 4096 (= 16 * 256).
- */
- *alignment = 1;
- size = align(size, 4096) + 16;
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
- case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
- /* element-size aligned for worst cases */
- *alignment = 16;
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_UNTYPED:
- /* DWord aligned? */
- *alignment = 4;
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_DATA:
- /* OWord aligned */
- *alignment = 16;
- size = align(size, 16);
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_SVB:
- /* always DWord aligned */
- *alignment = 4;
- break;
- default:
- assert(!"unknown access");
- *alignment = 1;
- break;
- }
-
- return size;
-}
-
-bool
-ilo_state_surface_init_for_null(struct ilo_state_surface *surf,
- const struct ilo_dev *dev)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(surf, sizeof(*surf)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= surface_set_gen7_null_SURFACE_STATE(surf, dev);
- else
- ret &= surface_set_gen6_null_SURFACE_STATE(surf, dev);
-
- surf->vma = NULL;
- surf->type = GEN6_SURFTYPE_NULL;
- surf->readonly = true;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_surface_init_for_buffer(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(surf, sizeof(*surf)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= surface_set_gen7_buffer_SURFACE_STATE(surf, dev, info);
- else
- ret &= surface_set_gen6_buffer_SURFACE_STATE(surf, dev, info);
-
- surf->vma = info->vma;
- surf->readonly = info->readonly;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_surface_init_for_image(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info)
-{
- bool ret = true;
-
- assert(ilo_is_zeroed(surf, sizeof(*surf)));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- ret &= surface_set_gen7_image_SURFACE_STATE(surf, dev, info);
- else
- ret &= surface_set_gen6_image_SURFACE_STATE(surf, dev, info);
-
- surf->vma = info->vma;
- surf->aux_vma = info->aux_vma;
-
- surf->is_integer = info->is_integer;
- surf->readonly = info->readonly;
- surf->scanout = info->img->scanout;
-
- assert(ret);
-
- return ret;
-}
-
-bool
-ilo_state_surface_set_scs(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- enum gen_surface_scs rgba[4])
-{
- const uint32_t scs = GEN_SHIFT32(rgba[0], GEN75_SURFACE_DW7_SCS_R) |
- GEN_SHIFT32(rgba[1], GEN75_SURFACE_DW7_SCS_G) |
- GEN_SHIFT32(rgba[2], GEN75_SURFACE_DW7_SCS_B) |
- GEN_SHIFT32(rgba[3], GEN75_SURFACE_DW7_SCS_A);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- assert(ilo_dev_gen(dev) >= ILO_GEN(7.5));
-
- surf->surface[7] = (surf->surface[7] & ~GEN75_SURFACE_DW7_SCS__MASK) | scs;
-
- return true;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_state_surface.h b/src/gallium/drivers/ilo/core/ilo_state_surface.h
deleted file mode 100644
index e78c7c97db1..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_surface.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#ifndef ILO_STATE_SURFACE_H
-#define ILO_STATE_SURFACE_H
-
-#include "genhw/genhw.h"
-
-#include "ilo_core.h"
-#include "ilo_dev.h"
-
-enum ilo_state_surface_access {
- ILO_STATE_SURFACE_ACCESS_SAMPLER, /* sampling engine surfaces */
- ILO_STATE_SURFACE_ACCESS_DP_RENDER, /* render target surfaces */
- ILO_STATE_SURFACE_ACCESS_DP_TYPED, /* typed surfaces */
- ILO_STATE_SURFACE_ACCESS_DP_UNTYPED, /* untyped surfaces */
- ILO_STATE_SURFACE_ACCESS_DP_DATA,
- ILO_STATE_SURFACE_ACCESS_DP_SVB,
-};
-
-struct ilo_vma;
-struct ilo_image;
-
-struct ilo_state_surface_buffer_info {
- const struct ilo_vma *vma;
- uint32_t offset;
- uint32_t size;
-
- enum ilo_state_surface_access access;
-
- /* format_size may be less than, equal to, or greater than struct_size */
- enum gen_surface_format format;
- uint8_t format_size;
-
- bool readonly;
- uint16_t struct_size;
-};
-
-struct ilo_state_surface_image_info {
- const struct ilo_image *img;
- uint8_t level_base;
- uint8_t level_count;
- uint16_t slice_base;
- uint16_t slice_count;
-
- const struct ilo_vma *vma;
- const struct ilo_vma *aux_vma;
-
- enum ilo_state_surface_access access;
-
- enum gen_surface_type type;
-
- enum gen_surface_format format;
- bool is_integer;
-
- bool readonly;
- bool is_array;
-};
-
-struct ilo_state_surface {
- uint32_t surface[13];
-
- const struct ilo_vma *vma;
- const struct ilo_vma *aux_vma;
-
- enum gen_surface_type type;
- uint8_t min_lod;
- uint8_t mip_count;
- bool is_integer;
-
- bool readonly;
- bool scanout;
-};
-
-bool
-ilo_state_surface_valid_format(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- enum gen_surface_format format);
-
-uint32_t
-ilo_state_surface_buffer_size(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- uint32_t size, uint32_t *alignment);
-
-bool
-ilo_state_surface_init_for_null(struct ilo_state_surface *surf,
- const struct ilo_dev *dev);
-
-bool
-ilo_state_surface_init_for_buffer(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_buffer_info *info);
-
-bool
-ilo_state_surface_init_for_image(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- const struct ilo_state_surface_image_info *info);
-
-bool
-ilo_state_surface_set_scs(struct ilo_state_surface *surf,
- const struct ilo_dev *dev,
- enum gen_surface_scs rgba[4]);
-
-#endif /* ILO_STATE_SURFACE_H */
diff --git a/src/gallium/drivers/ilo/core/ilo_state_surface_format.c b/src/gallium/drivers/ilo/core/ilo_state_surface_format.c
deleted file mode 100644
index a40c1b84d17..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_surface_format.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2013 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "genhw/genhw.h"
-#include "ilo_state_surface.h"
-
-static bool
-surface_valid_sampler_format(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- enum gen_surface_format format)
-{
- /*
- * This table is based on:
- *
- * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
- * - the Ivy Bridge PRM, volume 4 part 1, page 84-87
- */
- static const struct sampler_cap {
- int sampling;
- int filtering;
- int shadow_map;
- int chroma_key;
- } caps[] = {
-#define CAP(sampling, filtering, shadow_map, chroma_key) \
- { ILO_GEN(sampling), ILO_GEN(filtering), ILO_GEN(shadow_map), ILO_GEN(chroma_key) }
- [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32B32A32_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32B32A32_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32B32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32B32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32B32_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32B32_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R32G32_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32G32_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32_FLOAT_X8X24_TYPELESS] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_X32_TYPELESS_G8X24_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_L32A32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_R16G16B16X16_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16X16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_A32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_L32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_I32X32_FLOAT] = CAP( 1, 5, 0, 0),
- [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B8G8R8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R10G10B10A2_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R10G10B10A2_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R10G10B10A2_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R10G10B10_SNORM_A2_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8A8_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8A8_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8A8_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R8G8B8A8_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16G16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B10G10R10A2_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B10G10R10A2_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R11G11B10_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R32_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R32_FLOAT] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_R24_UNORM_X8_TYPELESS] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_X24_TYPELESS_G8_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_L16A16_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_I24X8_UNORM] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_L24X8_UNORM] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_A24X8_UNORM] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_I32_FLOAT] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_L32_FLOAT] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_A32_FLOAT] = CAP( 1, 5, 1, 0),
- [GEN6_FORMAT_B8G8R8X8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B8G8R8X8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8X8_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8B8X8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R9G9B9E5_SHAREDEXP] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B10G10R10X2_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_L16A16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B5G6R5_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B5G6R5_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B5G5R5A1_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B5G5R5A1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B4G4R4A4_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_B4G4R4A4_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8_SNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_R8G8_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R8G8_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16_UNORM] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_R16_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R16_FLOAT] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_A8P8_UNORM_PALETTE0] = CAP( 5, 5, 0, 0),
- [GEN6_FORMAT_A8P8_UNORM_PALETTE1] = CAP( 5, 5, 0, 0),
- [GEN6_FORMAT_I16_UNORM] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_L16_UNORM] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_A16_UNORM] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_L8A8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_I16_FLOAT] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_L16_FLOAT] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_A16_FLOAT] = CAP( 1, 1, 1, 0),
- [GEN6_FORMAT_L8A8_UNORM_SRGB] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_R5G5_SNORM_B6_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_P8A8_UNORM_PALETTE0] = CAP( 5, 5, 0, 0),
- [GEN6_FORMAT_P8A8_UNORM_PALETTE1] = CAP( 5, 5, 0, 0),
- [GEN6_FORMAT_R8_UNORM] = CAP( 1, 1, 0, 4.5),
- [GEN6_FORMAT_R8_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8_SINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_R8_UINT] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_A8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_I8_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_L8_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_P4A4_UNORM_PALETTE0] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_A4P4_UNORM_PALETTE0] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_P8_UNORM_PALETTE0] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_L8_UNORM_SRGB] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_P8_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_P4A4_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_A4P4_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_DXT1_RGB_SRGB] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_R1_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_YCRCB_NORMAL] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_YCRCB_SWAPUVY] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_P2_UNORM_PALETTE0] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_P2_UNORM_PALETTE1] = CAP(4.5, 4.5, 0, 0),
- [GEN6_FORMAT_BC1_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_BC2_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_BC3_UNORM] = CAP( 1, 1, 0, 1),
- [GEN6_FORMAT_BC4_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC5_UNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC2_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC3_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_MONO8] = CAP( 1, 0, 0, 0),
- [GEN6_FORMAT_YCRCB_SWAPUV] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_YCRCB_SWAPY] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_DXT1_RGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_FXT1] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC4_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_BC5_SNORM] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R16G16B16_FLOAT] = CAP( 5, 5, 0, 0),
- [GEN6_FORMAT_BC6H_SF16] = CAP( 7, 7, 0, 0),
- [GEN6_FORMAT_BC7_UNORM] = CAP( 7, 7, 0, 0),
- [GEN6_FORMAT_BC7_UNORM_SRGB] = CAP( 7, 7, 0, 0),
- [GEN6_FORMAT_BC6H_UF16] = CAP( 7, 7, 0, 0),
-#undef CAP
- };
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- return (format < ARRAY_SIZE(caps) && caps[format].sampling &&
- ilo_dev_gen(dev) >= caps[format].sampling);
-}
-
-static bool
-surface_valid_dp_format(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- enum gen_surface_format format)
-{
- /*
- * This table is based on:
- *
- * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
- * - the Ivy Bridge PRM, volume 4 part 1, page 172, 252-253, and 277-278
- * - the Haswell PRM, volume 7, page 262-264
- */
- static const struct dp_cap {
- int rt_write;
- int rt_write_blending;
- int typed_write;
- int media_color_processing;
- } caps[] = {
-#define CAP(rt_write, rt_write_blending, typed_write, media_color_processing) \
- { ILO_GEN(rt_write), ILO_GEN(rt_write_blending), ILO_GEN(typed_write), ILO_GEN(media_color_processing) }
- [GEN6_FORMAT_R32G32B32A32_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R32G32B32A32_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R32G32B32A32_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16B16A16_UNORM] = CAP( 1, 4.5, 7, 6),
- [GEN6_FORMAT_R16G16B16A16_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R16G16B16A16_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16B16A16_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16B16A16_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R32G32_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R32G32_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R32G32_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_B8G8R8A8_UNORM] = CAP( 1, 1, 7, 6),
- [GEN6_FORMAT_B8G8R8A8_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R10G10B10A2_UNORM] = CAP( 1, 1, 7, 6),
- [GEN6_FORMAT_R10G10B10A2_UNORM_SRGB] = CAP( 0, 0, 0, 6),
- [GEN6_FORMAT_R10G10B10A2_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R8G8B8A8_UNORM] = CAP( 1, 1, 7, 6),
- [GEN6_FORMAT_R8G8B8A8_UNORM_SRGB] = CAP( 1, 1, 0, 6),
- [GEN6_FORMAT_R8G8B8A8_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R8G8B8A8_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R8G8B8A8_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16_UNORM] = CAP( 1, 4.5, 7, 0),
- [GEN6_FORMAT_R16G16_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R16G16_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16G16_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B10G10R10A2_UNORM] = CAP( 1, 1, 7, 6),
- [GEN6_FORMAT_B10G10R10A2_UNORM_SRGB] = CAP( 1, 1, 0, 6),
- [GEN6_FORMAT_R11G11B10_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R32_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R32_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R32_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B8G8R8X8_UNORM] = CAP( 0, 0, 0, 6),
- [GEN6_FORMAT_B5G6R5_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B5G6R5_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B5G5R5A1_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B5G5R5A1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_B4G4R4A4_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B4G4R4A4_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8G8_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R8G8_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R8G8_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R8G8_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16_UNORM] = CAP( 1, 4.5, 7, 7),
- [GEN6_FORMAT_R16_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R16_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R16_FLOAT] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B5G5R5X1_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_B5G5R5X1_UNORM_SRGB] = CAP( 1, 1, 0, 0),
- [GEN6_FORMAT_R8_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_R8_SNORM] = CAP( 1, 6, 7, 0),
- [GEN6_FORMAT_R8_SINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_R8_UINT] = CAP( 1, 0, 7, 0),
- [GEN6_FORMAT_A8_UNORM] = CAP( 1, 1, 7, 0),
- [GEN6_FORMAT_YCRCB_NORMAL] = CAP( 1, 0, 0, 6),
- [GEN6_FORMAT_YCRCB_SWAPUVY] = CAP( 1, 0, 0, 6),
- [GEN6_FORMAT_YCRCB_SWAPUV] = CAP( 1, 0, 0, 6),
- [GEN6_FORMAT_YCRCB_SWAPY] = CAP( 1, 0, 0, 6),
-#undef CAP
- };
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (format >= ARRAY_SIZE(caps))
- return false;
-
- switch (access) {
- case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
- return (caps[format].rt_write &&
- ilo_dev_gen(dev) >= caps[format].rt_write);
- case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
- return (caps[format].typed_write &&
- ilo_dev_gen(dev) >= caps[format].typed_write);
- case ILO_STATE_SURFACE_ACCESS_DP_UNTYPED:
- return (format == GEN6_FORMAT_RAW);
- case ILO_STATE_SURFACE_ACCESS_DP_DATA:
- /* ignored, but can it be raw? */
- assert(format != GEN6_FORMAT_RAW);
- return true;
- default:
- return false;
- }
-}
-
-static bool
-surface_valid_svb_format(const struct ilo_dev *dev,
- enum gen_surface_format format)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- /*
- * This table is based on:
- *
- * - the Sandy Bridge PRM, volume 4 part 1, page 88-97
- * - the Ivy Bridge PRM, volume 2 part 1, page 195
- * - the Haswell PRM, volume 7, page 535
- */
- switch (format) {
- case GEN6_FORMAT_R32G32B32A32_FLOAT:
- case GEN6_FORMAT_R32G32B32A32_SINT:
- case GEN6_FORMAT_R32G32B32A32_UINT:
- case GEN6_FORMAT_R32G32B32_FLOAT:
- case GEN6_FORMAT_R32G32B32_SINT:
- case GEN6_FORMAT_R32G32B32_UINT:
- case GEN6_FORMAT_R32G32_FLOAT:
- case GEN6_FORMAT_R32G32_SINT:
- case GEN6_FORMAT_R32G32_UINT:
- case GEN6_FORMAT_R32_SINT:
- case GEN6_FORMAT_R32_UINT:
- case GEN6_FORMAT_R32_FLOAT:
- return true;
- default:
- return false;
- }
-}
-
-bool
-ilo_state_surface_valid_format(const struct ilo_dev *dev,
- enum ilo_state_surface_access access,
- enum gen_surface_format format)
-{
- bool valid;
-
- switch (access) {
- case ILO_STATE_SURFACE_ACCESS_SAMPLER:
- valid = surface_valid_sampler_format(dev, access, format);
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_RENDER:
- case ILO_STATE_SURFACE_ACCESS_DP_TYPED:
- case ILO_STATE_SURFACE_ACCESS_DP_UNTYPED:
- case ILO_STATE_SURFACE_ACCESS_DP_DATA:
- valid = surface_valid_dp_format(dev, access, format);
- break;
- case ILO_STATE_SURFACE_ACCESS_DP_SVB:
- valid = surface_valid_svb_format(dev, format);
- break;
- default:
- valid = false;
- break;
- }
-
- return valid;
-}
diff --git a/src/gallium/drivers/ilo/core/ilo_state_urb.c b/src/gallium/drivers/ilo/core/ilo_state_urb.c
deleted file mode 100644
index cbd150c71c9..00000000000
--- a/src/gallium/drivers/ilo/core/ilo_state_urb.c
+++ /dev/null
@@ -1,769 +0,0 @@
-/*
- * Mesa 3-D graphics library
- *
- * Copyright (C) 2012-2015 LunarG, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Chia-I Wu <olv@lunarg.com>
- */
-
-#include "ilo_debug.h"
-#include "ilo_state_urb.h"
-
-struct urb_configuration {
- uint8_t vs_pcb_alloc_kb;
- uint8_t hs_pcb_alloc_kb;
- uint8_t ds_pcb_alloc_kb;
- uint8_t gs_pcb_alloc_kb;
- uint8_t ps_pcb_alloc_kb;
-
- uint8_t urb_offset_8kb;
-
- uint8_t vs_urb_alloc_8kb;
- uint8_t hs_urb_alloc_8kb;
- uint8_t ds_urb_alloc_8kb;
- uint8_t gs_urb_alloc_8kb;
-
- uint8_t vs_entry_rows;
- uint8_t hs_entry_rows;
- uint8_t ds_entry_rows;
- uint8_t gs_entry_rows;
-
- int vs_entry_count;
- int hs_entry_count;
- int ds_entry_count;
- int gs_entry_count;
-};
-
-static void
-urb_alloc_gen7_pcb(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Haswell PRM, volume 2b, page 940:
- *
- * "[0,16] (0KB - 16KB) Increments of 1KB DevHSW:GT1, DevHSW:GT2
- * [0,32] (0KB - 32KB) Increments of 2KB DevHSW:GT3"
- */
- const uint8_t increment_kb =
- (ilo_dev_gen(dev) >= ILO_GEN(8) ||
- (ilo_dev_gen(dev) == ILO_GEN(7.5) && dev->gt == 3)) ? 2 : 1;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * Keep the strategy simple as we do not know the workloads and how
- * expensive it is to change the configuration frequently.
- */
- if (info->hs_const_data || info->ds_const_data) {
- conf->vs_pcb_alloc_kb = increment_kb * 4;
- conf->hs_pcb_alloc_kb = increment_kb * 3;
- conf->ds_pcb_alloc_kb = increment_kb * 3;
- conf->gs_pcb_alloc_kb = increment_kb * 3;
- conf->ps_pcb_alloc_kb = increment_kb * 3;
- } else if (info->gs_const_data) {
- conf->vs_pcb_alloc_kb = increment_kb * 6;
- conf->gs_pcb_alloc_kb = increment_kb * 5;
- conf->ps_pcb_alloc_kb = increment_kb * 5;
- } else {
- conf->vs_pcb_alloc_kb = increment_kb * 8;
- conf->ps_pcb_alloc_kb = increment_kb * 8;
- }
-
- conf->urb_offset_8kb = increment_kb * 16 / 8;
-}
-
-static void
-urb_alloc_gen6_urb(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 34:
- *
- * "(VS URB Starting Address) Offset from the start of the URB memory
- * where VS starts its allocation, specified in multiples of 8 KB."
- *
- * Same for other stages.
- */
- const int space_avail_8kb = dev->urb_size / 8192 - conf->urb_offset_8kb;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 173:
- *
- * "Programming Note: If the GS stage is enabled, software must always
- * allocate at least one GS URB Entry. This is true even if the GS
- * thread never needs to output vertices to the urb, e.g., when only
- * performing stream output. This is an artifact of the need to pass
- * the GS thread an initial destination URB handle."
- */
- const bool force_gs_alloc =
- (ilo_dev_gen(dev) == ILO_GEN(6) && info->gs_enable);
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (info->hs_entry_size || info->ds_entry_size) {
- conf->vs_urb_alloc_8kb = space_avail_8kb / 4;
- conf->hs_urb_alloc_8kb = space_avail_8kb / 4;
- conf->ds_urb_alloc_8kb = space_avail_8kb / 4;
- conf->gs_urb_alloc_8kb = space_avail_8kb / 4;
-
- if (space_avail_8kb % 4) {
- assert(space_avail_8kb % 2 == 0);
- conf->vs_urb_alloc_8kb++;
- conf->gs_urb_alloc_8kb++;
- }
- } else if (info->gs_entry_size || force_gs_alloc) {
- assert(space_avail_8kb % 2 == 0);
- conf->vs_urb_alloc_8kb = space_avail_8kb / 2;
- conf->gs_urb_alloc_8kb = space_avail_8kb / 2;
- } else {
- conf->vs_urb_alloc_8kb = space_avail_8kb;
- }
-}
-
-static bool
-urb_init_gen6_vs_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 28:
- *
- * "(VS URB Entry Allocation Size)
- * Range [0,4] = [1,5] 1024-bit URB rows"
- *
- * "(VS Number of URB Entries)
- * Range [24,256] in multiples of 4
- * [24, 128] in multiples of 4[DevSNBGT1]"
- */
- const int max_entry_count = (dev->gt == 2) ? 256 : 252;
- const int row_size = 1024 / 8;
- int row_count, entry_count;
- int entry_size;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- /* VE and VS share the same VUE for each vertex */
- entry_size = info->vs_entry_size;
- if (entry_size < info->ve_entry_size)
- entry_size = info->ve_entry_size;
-
- row_count = (entry_size + row_size - 1) / row_size;
- if (row_count > 5)
- return false;
- else if (!row_count)
- row_count++;
-
- entry_count = conf->vs_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- entry_count &= ~3;
- assert(entry_count >= 24);
-
- conf->vs_entry_rows = row_count;
- conf->vs_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_init_gen6_gs_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 29:
- *
- * "(GS Number of URB Entries)
- * Range [0,256] in multiples of 4
- * [0, 254] in multiples of 4[DevSNBGT1]"
- *
- * "(GS URB Entry Allocation Size)
- * Range [0,4] = [1,5] 1024-bit URB rows"
- */
- const int max_entry_count = (dev->gt == 2) ? 256 : 252;
- const int row_size = 1024 / 8;
- int row_count, entry_count;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- row_count = (info->gs_entry_size + row_size - 1) / row_size;
- if (row_count > 5)
- return false;
- else if (!row_count)
- row_count++;
-
- entry_count = conf->gs_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- entry_count &= ~3;
-
- conf->gs_entry_rows = row_count;
- conf->gs_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_init_gen7_vs_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 34-35:
- *
- * "VS URB Entry Allocation Size equal to 4(5 512-bit URB rows) may
- * cause performance to decrease due to banking in the URB. Element
- * sizes of 16 to 20 should be programmed with six 512-bit URB rows."
- *
- * "(VS URB Entry Allocation Size)
- * Format: U9-1 count of 512-bit units"
- *
- * "(VS Number of URB Entries)
- * [32,704]
- * [32,512]
- *
- * Programming Restriction: VS Number of URB Entries must be divisible
- * by 8 if the VS URB Entry Allocation Size is less than 9 512-bit URB
- * entries."2:0" = reserved "000b""
- *
- * From the Haswell PRM, volume 2b, page 847:
- *
- * "(VS Number of URB Entries)
- * [64,1664] DevHSW:GT3
- * [64,1664] DevHSW:GT2
- * [32,640] DevHSW:GT1"
- */
- const int row_size = 512 / 8;
- int row_count, entry_count;
- int entry_size;
- int max_entry_count, min_entry_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 35:
- *
- * "Programming Restriction: As the VS URB entry serves as both the
- * per-vertex input and output of the VS shader, the VS URB Allocation
- * Size must be sized to the maximum of the vertex input and output
- * structures."
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 42:
- *
- * "If the VS function is enabled, the VF-written VUEs are not required
- * to have Vertex Headers, as the VS-incoming vertices are guaranteed
- * to be consumed by the VS (i.e., the VS thread is responsible for
- * overwriting the input vertex data)."
- *
- * VE and VS share the same VUE for each vertex.
- */
- entry_size = info->vs_entry_size;
- if (entry_size < info->ve_entry_size)
- entry_size = info->ve_entry_size;
-
- row_count = (entry_size + row_size - 1) / row_size;
- if (row_count == 5 || !row_count)
- row_count++;
-
- entry_count = conf->vs_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (row_count < 9)
- entry_count &= ~7;
-
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- case ILO_GEN(7.5):
- max_entry_count = (dev->gt >= 2) ? 1664 : 640;
- min_entry_count = (dev->gt >= 2) ? 64 : 32;
- break;
- case ILO_GEN(7):
- max_entry_count = (dev->gt == 2) ? 704 : 512;
- min_entry_count = 32;
- break;
- default:
- assert(!"unexpected gen");
- return false;
- break;
- }
-
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- else if (entry_count < min_entry_count)
- return false;
-
- conf->vs_entry_rows = row_count;
- conf->vs_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_init_gen7_hs_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 37:
- *
- * "HS Number of URB Entries must be divisible by 8 if the HS URB Entry
- * Allocation Size is less than 9 512-bit URB
- * entries."2:0" = reserved "000"
- *
- * [0,64]
- * [0,32]"
- *
- * From the Haswell PRM, volume 2b, page 849:
- *
- * "(HS Number of URB Entries)
- * [0,128] DevHSW:GT2
- * [0,64] DevHSW:GT1"
- */
- const int row_size = 512 / 8;
- int row_count, entry_count;
- int max_entry_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- row_count = (info->hs_entry_size + row_size - 1) / row_size;
- if (!row_count)
- row_count++;
-
- entry_count = conf->hs_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (row_count < 9)
- entry_count &= ~7;
-
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- case ILO_GEN(7.5):
- max_entry_count = (dev->gt >= 2) ? 128 : 64;
- break;
- case ILO_GEN(7):
- max_entry_count = (dev->gt == 2) ? 64 : 32;
- break;
- default:
- assert(!"unexpected gen");
- return false;
- break;
- }
-
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- else if (info->hs_entry_size && !entry_count)
- return false;
-
- conf->hs_entry_rows = row_count;
- conf->hs_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_init_gen7_ds_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 38:
- *
- * "(DS URB Entry Allocation Size)
- * [0,9]"
- *
- * "(DS Number of URB Entries) If Domain Shader Thread Dispatch is
- * Enabled then the minimum number handles that must be allocated is
- * 138 URB entries.
- * "2:0" = reserved "000"
- *
- * [0,448]
- * [0,288]
- *
- * DS Number of URB Entries must be divisible by 8 if the DS URB Entry
- * Allocation Size is less than 9 512-bit URB entries.If Domain Shader
- * Thread Dispatch is Enabled then the minimum number of handles that
- * must be allocated is 10 URB entries."
- *
- * From the Haswell PRM, volume 2b, page 851:
- *
- * "(DS Number of URB Entries)
- * [0,960] DevHSW:GT2
- * [0,384] DevHSW:GT1"
- */
- const int row_size = 512 / 8;
- int row_count, entry_count;
- int max_entry_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- row_count = (info->ds_entry_size + row_size - 1) / row_size;
- if (row_count > 10)
- return false;
- else if (!row_count)
- row_count++;
-
- entry_count = conf->ds_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (row_count < 9)
- entry_count &= ~7;
-
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- case ILO_GEN(7.5):
- max_entry_count = (dev->gt >= 2) ? 960 : 384;
- break;
- case ILO_GEN(7):
- max_entry_count = (dev->gt == 2) ? 448 : 288;
- break;
- default:
- assert(!"unexpected gen");
- return false;
- break;
- }
-
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- else if (info->ds_entry_size && entry_count < 10)
- return false;
-
- conf->ds_entry_rows = row_count;
- conf->ds_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_init_gen7_gs_entry(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 40:
- *
- * "(GS Number of URB Entries) GS Number of URB Entries must be
- * divisible by 8 if the GS URB Entry Allocation Size is less than 9
- * 512-bit URB entries.
- * "2:0" = reserved "000"
- *
- * [0,320]
- * [0,192]"
- *
- * From the Ivy Bridge PRM, volume 2 part 1, page 171:
- *
- * "(DUAL_INSTANCE and DUAL_OBJECT) The GS must be allocated at least
- * two URB handles or behavior is UNDEFINED."
- *
- * From the Haswell PRM, volume 2b, page 853:
- *
- * "(GS Number of URB Entries)
- * [0,640] DevHSW:GT2
- * [0,256] DevHSW:GT1
- *
- * Only if GS is disabled can this field be programmed to 0. If GS is
- * enabled this field shall be programmed to a value greater than 0.
- * For GS Dispatch Mode "Single", this field shall be programmed to a
- * value greater than or equal to 1. For other GS Dispatch Modes,
- * refer to the definition of Dispatch Mode (3DSTATE_GS) for minimum
- * values of this field."
- */
- const int row_size = 512 / 8;
- int row_count, entry_count;
- int max_entry_count;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- row_count = (info->gs_entry_size + row_size - 1) / row_size;
- if (!row_count)
- row_count++;
-
- entry_count = conf->gs_urb_alloc_8kb * 8192 / (row_size * row_count);
- if (row_count < 9)
- entry_count &= ~7;
-
- switch (ilo_dev_gen(dev)) {
- case ILO_GEN(8):
- case ILO_GEN(7.5):
- max_entry_count = (dev->gt >= 2) ? 640 : 256;
- break;
- case ILO_GEN(7):
- max_entry_count = (dev->gt == 2) ? 320 : 192;
- break;
- default:
- assert(!"unexpected gen");
- return false;
- break;
- }
-
- if (entry_count > max_entry_count)
- entry_count = max_entry_count;
- else if (info->gs_entry_size && entry_count < 2)
- return false;
-
- conf->gs_entry_rows = row_count;
- conf->gs_entry_count = entry_count;
-
- return true;
-}
-
-static bool
-urb_get_gen6_configuration(const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- struct urb_configuration *conf)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- memset(conf, 0, sizeof(*conf));
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7))
- urb_alloc_gen7_pcb(dev, info, conf);
-
- urb_alloc_gen6_urb(dev, info, conf);
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- if (!urb_init_gen7_vs_entry(dev, info, conf) ||
- !urb_init_gen7_hs_entry(dev, info, conf) ||
- !urb_init_gen7_ds_entry(dev, info, conf) ||
- !urb_init_gen7_gs_entry(dev, info, conf))
- return false;
- } else {
- if (!urb_init_gen6_vs_entry(dev, info, conf) ||
- !urb_init_gen6_gs_entry(dev, info, conf))
- return false;
- }
-
- return true;
-}
-
-static bool
-urb_set_gen7_3dstate_push_constant_alloc(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- const struct urb_configuration *conf)
-{
- uint32_t dw1[5];
- uint8_t sizes_kb[5], offset_kb;
- int i;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- sizes_kb[0] = conf->vs_pcb_alloc_kb;
- sizes_kb[1] = conf->hs_pcb_alloc_kb;
- sizes_kb[2] = conf->ds_pcb_alloc_kb;
- sizes_kb[3] = conf->gs_pcb_alloc_kb;
- sizes_kb[4] = conf->ps_pcb_alloc_kb;
- offset_kb = 0;
-
- for (i = 0; i < 5; i++) {
- /* careful for the valid range of offsets */
- if (sizes_kb[i]) {
- dw1[i] = offset_kb << GEN7_PCB_ALLOC_DW1_OFFSET__SHIFT |
- sizes_kb[i] << GEN7_PCB_ALLOC_DW1_SIZE__SHIFT;
- offset_kb += sizes_kb[i];
- } else {
- dw1[i] = 0;
- }
- }
-
- STATIC_ASSERT(ARRAY_SIZE(urb->pcb) >= 5);
- memcpy(urb->pcb, dw1, sizeof(dw1));
-
- return true;
-}
-
-static bool
-urb_set_gen6_3DSTATE_URB(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- const struct urb_configuration *conf)
-{
- uint32_t dw1, dw2;
-
- ILO_DEV_ASSERT(dev, 6, 6);
-
- assert(conf->vs_entry_rows && conf->gs_entry_rows);
-
- dw1 = (conf->vs_entry_rows - 1) << GEN6_URB_DW1_VS_ENTRY_SIZE__SHIFT |
- conf->vs_entry_count << GEN6_URB_DW1_VS_ENTRY_COUNT__SHIFT;
- dw2 = conf->gs_entry_count << GEN6_URB_DW2_GS_ENTRY_COUNT__SHIFT |
- (conf->gs_entry_rows - 1) << GEN6_URB_DW2_GS_ENTRY_SIZE__SHIFT;
-
- STATIC_ASSERT(ARRAY_SIZE(urb->urb) >= 2);
- urb->urb[0] = dw1;
- urb->urb[1] = dw2;
-
- return true;
-}
-
-static bool
-urb_set_gen7_3dstate_urb(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info,
- const struct urb_configuration *conf)
-{
- uint32_t dw1[4];
- struct {
- uint8_t alloc_8kb;
- uint8_t entry_rows;
- int entry_count;
- } stages[4];
- uint8_t offset_8kb;
- int i;
-
- ILO_DEV_ASSERT(dev, 7, 8);
-
- stages[0].alloc_8kb = conf->vs_urb_alloc_8kb;
- stages[1].alloc_8kb = conf->hs_urb_alloc_8kb;
- stages[2].alloc_8kb = conf->ds_urb_alloc_8kb;
- stages[3].alloc_8kb = conf->gs_urb_alloc_8kb;
-
- stages[0].entry_rows = conf->vs_entry_rows;
- stages[1].entry_rows = conf->hs_entry_rows;
- stages[2].entry_rows = conf->ds_entry_rows;
- stages[3].entry_rows = conf->gs_entry_rows;
-
- stages[0].entry_count = conf->vs_entry_count;
- stages[1].entry_count = conf->hs_entry_count;
- stages[2].entry_count = conf->ds_entry_count;
- stages[3].entry_count = conf->gs_entry_count;
-
- offset_8kb = conf->urb_offset_8kb;
-
- for (i = 0; i < 4; i++) {
- /* careful for the valid range of offsets */
- if (stages[i].alloc_8kb) {
- assert(stages[i].entry_rows);
- dw1[i] =
- offset_8kb << GEN7_URB_DW1_OFFSET__SHIFT |
- (stages[i].entry_rows - 1) << GEN7_URB_DW1_ENTRY_SIZE__SHIFT |
- stages[i].entry_count << GEN7_URB_DW1_ENTRY_COUNT__SHIFT;
- offset_8kb += stages[i].alloc_8kb;
- } else {
- dw1[i] = 0;
- }
- }
-
- STATIC_ASSERT(ARRAY_SIZE(urb->urb) >= 4);
- memcpy(urb->urb, dw1, sizeof(dw1));
-
- return true;
-}
-
-bool
-ilo_state_urb_init(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info)
-{
- assert(ilo_is_zeroed(urb, sizeof(*urb)));
- return ilo_state_urb_set_info(urb, dev, info);
-}
-
-bool
-ilo_state_urb_init_for_rectlist(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- uint8_t vf_attr_count)
-{
- struct ilo_state_urb_info info;
-
- memset(&info, 0, sizeof(info));
- info.ve_entry_size = sizeof(uint32_t) * 4 * vf_attr_count;
-
- return ilo_state_urb_init(urb, dev, &info);
-}
-
-bool
-ilo_state_urb_set_info(struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb_info *info)
-{
- struct urb_configuration conf;
- bool ret = true;
-
- ret &= urb_get_gen6_configuration(dev, info, &conf);
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- ret &= urb_set_gen7_3dstate_push_constant_alloc(urb, dev, info, &conf);
- ret &= urb_set_gen7_3dstate_urb(urb, dev, info, &conf);
- } else {
- ret &= urb_set_gen6_3DSTATE_URB(urb, dev, info, &conf);
- }
-
- assert(ret);
-
- return ret;
-}
-
-void
-ilo_state_urb_full_delta(const struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- struct ilo_state_urb_delta *delta)
-{
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- delta->dirty = ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_VS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_HS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_DS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_GS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_PS |
- ILO_STATE_URB_3DSTATE_URB_VS |
- ILO_STATE_URB_3DSTATE_URB_HS |
- ILO_STATE_URB_3DSTATE_URB_DS |
- ILO_STATE_URB_3DSTATE_URB_GS;
- } else {
- delta->dirty = ILO_STATE_URB_3DSTATE_URB_VS |
- ILO_STATE_URB_3DSTATE_URB_GS;
- }
-}
-
-void
-ilo_state_urb_get_delta(const struct ilo_state_urb *urb,
- const struct ilo_dev *dev,
- const struct ilo_state_urb *old,
- struct ilo_state_urb_delta *delta)
-{
- delta->dirty = 0;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- if (memcmp(urb->pcb, old->pcb, sizeof(urb->pcb))) {
- delta->dirty |= ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_VS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_HS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_DS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_GS |
- ILO_STATE_URB_3DSTATE_PUSH_CONSTANT_ALLOC_PS;
- }
-
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 34:
- *
- * "3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
- * programmed in order for the programming of this state
- * (3DSTATE_URB_VS) to be valid."
- *
- * The same is true for the other three states.
- */
- if (memcmp(urb->urb, old->urb, sizeof(urb->urb))) {
- delta->dirty |= ILO_STATE_URB_3DSTATE_URB_VS |
- ILO_STATE_URB_3DSTATE_URB_HS |
- ILO_STATE_URB_3DSTATE_URB_DS |
- ILO_STATE_URB_3DSTATE_URB_GS;
- }
- } else {
- if