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authorMarek Olšák <marek.olsak@amd.com>2019-02-07 00:04:32 -0500
committerMarek Olšák <marek.olsak@amd.com>2019-07-29 17:52:51 -0400
commit19d04191c4e7c2022fb3534d94ad21683feb1604 (patch)
treeda9326420175a619033d59849ebe06861d48c161
parentc82f33885574e0f8199415b79d6f2b812360b969 (diff)
radeonsi: add support for compute-only chips
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
-rw-r--r--src/amd/common/ac_gpu_info.c1
-rw-r--r--src/amd/common/ac_gpu_info.h1
-rw-r--r--src/amd/common/ac_surface.c5
-rw-r--r--src/gallium/drivers/radeonsi/si_get.c5
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c15
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c1
6 files changed, 22 insertions, 6 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index a501d840b25..f1f31e55abe 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -436,6 +436,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
+ info->has_graphics = gfx.available_rings > 0;
info->num_sdma_rings = util_bitcount(dma.available_rings);
info->num_compute_rings = util_bitcount(compute.available_rings);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 3ec3e44d665..8418a62e387 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -53,6 +53,7 @@ struct radeon_info {
enum chip_class chip_class;
uint32_t family_id;
uint32_t chip_external_rev;
+ bool has_graphics; /* false if the chip is compute-only */
uint32_t num_compute_rings;
uint32_t num_sdma_rings;
uint32_t clock_crystal_freq;
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 7d871c47204..53353cdee18 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -658,6 +658,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
*/
AddrSurfInfoIn.flags.dccCompatible =
info->chip_class >= GFX8 &&
+ info->has_graphics && /* disable DCC on compute-only chips */
!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
!compressed &&
@@ -1122,7 +1123,9 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
}
/* DCC */
- if (!(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed &&
+ if (info->has_graphics &&
+ !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
+ !compressed &&
gfx9_is_dcc_capable(info, in->swizzleMode)) {
ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index 882bbbbae06..85807db0e1c 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -157,7 +157,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
case PIPE_CAP_IMAGE_LOAD_FORMATTED:
case PIPE_CAP_PREFER_COMPUTE_BLIT_FOR_MULTIMEDIA:
- case PIPE_CAP_TGSI_DIV:
+ case PIPE_CAP_TGSI_DIV:
return 1;
case PIPE_CAP_QUERY_SO_OVERFLOW:
@@ -166,6 +166,9 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_POST_DEPTH_COVERAGE:
return sscreen->info.chip_class >= GFX10;
+ case PIPE_CAP_GRAPHICS:
+ return sscreen->info.has_graphics;
+
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 96c71d91bd5..0140729d247 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -392,8 +392,14 @@ static void si_set_context_param(struct pipe_context *ctx,
static struct pipe_context *si_create_context(struct pipe_screen *screen,
unsigned flags)
{
- struct si_context *sctx = CALLOC_STRUCT(si_context);
struct si_screen* sscreen = (struct si_screen *)screen;
+
+ /* Don't create a context if it's not compute-only and hw is compute-only. */
+ if (!sscreen->info.has_graphics &&
+ !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
+ return NULL;
+
+ struct si_context *sctx = CALLOC_STRUCT(si_context);
struct radeon_winsys *ws = sscreen->ws;
int shader, i;
bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
@@ -520,10 +526,10 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
si_init_fence_functions(sctx);
si_init_query_functions(sctx);
si_init_state_compute_functions(sctx);
+ si_init_context_texture_functions(sctx);
/* Initialize graphics-only context functions. */
if (sctx->has_graphics) {
- si_init_context_texture_functions(sctx);
if (sctx->chip_class >= GFX10)
gfx10_init_query(sctx);
si_init_msaa_functions(sctx);
@@ -1251,8 +1257,9 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
}
/* Create the auxiliary context. This must be done last. */
- sscreen->aux_context = si_create_context(
- &sscreen->b, sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0);
+ sscreen->aux_context = si_create_context(&sscreen->b,
+ (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
+ (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
if (sscreen->options.aux_debug) {
struct u_log_context *log = CALLOC_STRUCT(u_log_context);
u_log_context_init(log);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index c30b40376a2..07f8318d94a 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -587,6 +587,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.has_2d_tiling = ws->info.chip_class <= GFX6 || ws->info.drm_minor >= 35;
ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
ws->info.max_alignment = 1024*1024;
+ ws->info.has_graphics = true;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;