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authorRhys Perry <pendingchaos02@gmail.com>2019-11-27 17:24:23 +0000
committerRhys Perry <pendingchaos02@gmail.com>2019-11-29 17:46:01 +0000
commit11f43caaeca166c96ae49dbd506b6f58dd4a13fb (patch)
tree7c420cb05b9f269d2be38ea3da605cd55a781bbe
parentff70ccad16a2efb3be1fbc4ca03453d38721a267 (diff)
aco: fix i2i64
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler') Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
-rw-r--r--src/amd/compiler/aco_instruction_selection.cpp8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index bcccd0435f1..cb33814f17f 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -2033,8 +2033,12 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
}
case nir_op_i2i64: {
Temp src = get_alu_src(ctx, instr->src[0]);
- if (instr->src[0].src.ssa->bit_size == 32) {
- bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
+ if (src.regClass() == s1) {
+ Temp high = bld.sopc(aco_opcode::s_ashr_i32, bld.def(s1, scc), src, Operand(31u));
+ bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
+ } else if (src.regClass() == v1) {
+ Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
+ bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
} else {
fprintf(stderr, "Unimplemented NIR instr bit size: ");
nir_print_instr(&instr->instr, stderr);