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authorKevin Rogovin <kevin.rogovin@intel.com>2018-08-27 09:54:24 +0300
committerPlamena Manolova <plamena.n.manolova@gmail.com>2018-08-28 17:15:10 +0300
commit03ecec9ed2099f6e2b62994b33dc948dc731e7b8 (patch)
tree69549844e81bb93aee07e3cfc2195c68b2d3c62c
parent119435c8778dd26cb7c8bcde9f04b3982239fe60 (diff)
i965: Add INTEL_fragment_shader_ordering support.
Adds suppport for INTEL_fragment_shader_ordering. We achieve the fragment ordering by using the same instruction as for beginInvocationInterlockARB() which is by issuing a memory fence via sendc. Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com> Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
-rw-r--r--docs/relnotes/18.3.0.html1
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp1
-rw-r--r--src/mesa/drivers/dri/i965/intel_extensions.c1
3 files changed, 3 insertions, 0 deletions
diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
index afcb0448177..71fb41ca86f 100644
--- a/docs/relnotes/18.3.0.html
+++ b/docs/relnotes/18.3.0.html
@@ -59,6 +59,7 @@ Note: some of the new features are only available with certain drivers.
<li>GL_EXT_vertex_attrib_64bit on i965, nvc0, radeonsi.</li>
<li>GL_EXT_window_rectangles on radeonsi.</li>
<li>GL_KHR_texture_compression_astc_sliced_3d on radeonsi.</li>
+<li>GL_INTEL_fragment_shader_ordering on i965.</li>
<li>GL_NV_fragment_shader_interlock on i965.</li>
</ul>
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 9c9df5ac09f..62bff2a323a 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4836,6 +4836,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
break;
}
+ case nir_intrinsic_begin_fragment_shader_ordering:
case nir_intrinsic_begin_invocation_interlock: {
const fs_builder ubld = bld.group(8, 0);
const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2);
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c
index 0b137664b0d..1ea8594c348 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -247,6 +247,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.OES_primitive_bounding_box = true;
ctx->Extensions.OES_texture_buffer = true;
ctx->Extensions.ARB_fragment_shader_interlock = true;
+ ctx->Extensions.INTEL_fragment_shader_ordering = true;
if (can_do_pipelined_register_writes(brw->screen)) {
ctx->Extensions.ARB_draw_indirect = true;