diff options
| author | Marcin Ślusarz <marcin.slusarz@intel.com> | 2022-05-23 17:09:33 +0200 |
|---|---|---|
| committer | Dylan Baker <dylan.c.baker@intel.com> | 2022-06-27 09:18:27 -0700 |
| commit | a21cba54cac84e94ef663a43ed0b8bc1a604eeca (patch) | |
| tree | 6f5457d35ae0ee173782406b80a233c267e9dbb5 | |
| parent | 02923d768501d596171a3ecaef0946c41aed4423 (diff) | |
intel/compiler: adjust task payload offsets as late as possiblestaging/22.1
Otherwise passes which expect offsets to be in bytes (like
brw_nir_lower_mem_access_bit_sizes, called from brw_postprocess_nir)
may produce incorrect results.
Fixes 64-bit load/stores in task/mesh shaders.
Fixes: c36ae42e4cc ("intel/compiler: Use nir_var_mem_task_payload")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16196>
(cherry picked from commit 42b551fe7f970c8fd6e530e3d2169abb934c72c2)
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/intel/compiler/brw_mesh.cpp | 29 |
2 files changed, 23 insertions, 8 deletions
diff --git a/.pick_status.json b/.pick_status.json index 8bb44c8b8d7..3d0bbb00589 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -76,7 +76,7 @@ "description": "intel/compiler: adjust task payload offsets as late as possible", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "c36ae42e4cccc925e5319afe41c4b8ba850730b4" }, diff --git a/src/intel/compiler/brw_mesh.cpp b/src/intel/compiler/brw_mesh.cpp index 0f177f55a3c..aef2adc5cdf 100644 --- a/src/intel/compiler/brw_mesh.cpp +++ b/src/intel/compiler/brw_mesh.cpp @@ -171,13 +171,26 @@ brw_nir_adjust_task_payload_offsets_instr(struct nir_builder *b, } } -static void +static bool brw_nir_adjust_task_payload_offsets(nir_shader *nir) { - nir_shader_instructions_pass(nir, brw_nir_adjust_task_payload_offsets_instr, - nir_metadata_block_index | - nir_metadata_dominance, - NULL); + return nir_shader_instructions_pass(nir, + brw_nir_adjust_task_payload_offsets_instr, + nir_metadata_block_index | + nir_metadata_dominance, + NULL); +} + +static void +brw_nir_adjust_payload(nir_shader *shader, const struct brw_compiler *compiler) +{ + /* Adjustment of task payload offsets must be performed *after* last pass + * which interprets them as bytes, because it changes their unit. + */ + bool adjusted = false; + NIR_PASS(adjusted, shader, brw_nir_adjust_task_payload_offsets); + if (adjusted) /* clean up the mess created by offset adjustments */ + NIR_PASS_V(shader, nir_opt_constant_folding); } const unsigned * @@ -202,7 +215,6 @@ brw_compile_task(const struct brw_compiler *compiler, BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID); NIR_PASS_V(nir, brw_nir_lower_tue_outputs, &prog_data->map); - NIR_PASS_V(nir, brw_nir_adjust_task_payload_offsets); const unsigned required_dispatch_width = brw_required_dispatch_width(&nir->info, key->base.subgroup_size_type); @@ -226,6 +238,8 @@ brw_compile_task(const struct brw_compiler *compiler, brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled, key->base.robust_buffer_access); + brw_nir_adjust_payload(shader, compiler); + v[simd] = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base, &prog_data->base.base, shader, dispatch_width, debug_enabled); @@ -686,7 +700,6 @@ brw_compile_mesh(const struct brw_compiler *compiler, BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID); NIR_PASS_V(nir, brw_nir_lower_tue_inputs, params->tue_map); - NIR_PASS_V(nir, brw_nir_adjust_task_payload_offsets); brw_compute_mue_map(nir, &prog_data->map); NIR_PASS_V(nir, brw_nir_lower_mue_outputs, &prog_data->map); @@ -725,6 +738,8 @@ brw_compile_mesh(const struct brw_compiler *compiler, brw_postprocess_nir(shader, compiler, true /* is_scalar */, debug_enabled, key->base.robust_buffer_access); + brw_nir_adjust_payload(shader, compiler); + v[simd] = new fs_visitor(compiler, params->log_data, mem_ctx, &key->base, &prog_data->base.base, shader, dispatch_width, debug_enabled); |