diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2012-10-03 14:26:29 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-04-16 15:08:12 -0700 |
| commit | e7965598b7cc1123847e5c87ab16745145e849e2 (patch) | |
| tree | 854bb67305c56c7aa6aade4d40141100e21feba2 | |
| parent | 13ddf9baf27e4c460df83a033ad618d65b61ab8f (diff) | |
i965: Enable the Bay Trail platform.
This patch adds PCI IDs for Bay Trail (sometimes called Valley View).
As far as the 3D driver is concerned, it's very similar to Ivybridge,
so the existing code should work just fine.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
| -rw-r--r-- | include/pci_ids/i965_pci_ids.h | 5 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_chipset.h | 13 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.c | 10 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.h | 1 |
4 files changed, 29 insertions, 0 deletions
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 1e388f8cadd..9a2da61357e 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -62,3 +62,8 @@ CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1) CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2) CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0F31, BAYTRAIL_M_1, byt) +CHIPSET(0x0F32, BAYTRAIL_M_2, byt) +CHIPSET(0x0F33, BAYTRAIL_M_3, byt) +CHIPSET(0x0157, BAYTRAIL_M_4, byt) +CHIPSET(0x0155, BAYTRAIL_D, byt) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 885f6c2d32c..04753ddb631 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -87,6 +87,12 @@ #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */ #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a +#define PCI_CHIP_BAYTRAIL_M_1 0x0F31 +#define PCI_CHIP_BAYTRAIL_M_2 0x0F32 +#define PCI_CHIP_BAYTRAIL_M_3 0x0F33 +#define PCI_CHIP_BAYTRAIL_M_4 0x0157 +#define PCI_CHIP_BAYTRAIL_D 0x0155 + #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ #define PCI_CHIP_HASWELL_GT2 0x0412 #define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 @@ -190,7 +196,14 @@ #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || IS_IVB_GT2(devid)) +#define IS_BAYTRAIL(devid) (devid == PCI_CHIP_BAYTRAIL_M_1 || \ + devid == PCI_CHIP_BAYTRAIL_M_2 || \ + devid == PCI_CHIP_BAYTRAIL_M_3 || \ + devid == PCI_CHIP_BAYTRAIL_M_4 || \ + devid == PCI_CHIP_BAYTRAIL_D) + #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ + IS_BAYTRAIL(devid) || \ IS_HASWELL(devid)) #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index ba7d4b631f3..0a1dd7501de 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -186,6 +186,13 @@ intelGetString(struct gl_context * ctx, GLenum name) case PCI_CHIP_IVYBRIDGE_S_GT2: chipset = "Intel(R) Ivybridge Server"; break; + case PCI_CHIP_BAYTRAIL_M_1: + case PCI_CHIP_BAYTRAIL_M_2: + case PCI_CHIP_BAYTRAIL_M_3: + case PCI_CHIP_BAYTRAIL_M_4: + case PCI_CHIP_BAYTRAIL_D: + chipset = "Intel(R) Bay Trail"; + break; case PCI_CHIP_HASWELL_GT1: case PCI_CHIP_HASWELL_GT2: case PCI_CHIP_HASWELL_GT2_PLUS: @@ -682,6 +689,9 @@ intelInitContext(struct intel_context *intel, if (IS_HASWELL(devID)) { intel->is_haswell = true; + } else if (IS_BAYTRAIL(devID)) { + intel->is_baytrail = true; + intel->gt = 1; } else if (IS_G4X(devID)) { intel->is_g4x = true; } else if (IS_945(devID)) { diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 4591ab73c0c..c0f07ff1f3c 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -236,6 +236,7 @@ struct intel_context int gt; bool needs_ff_sync; bool is_haswell; + bool is_baytrail; bool is_g4x; bool is_945; bool has_separate_stencil; |