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authorKenneth Graunke <kenneth@whitecape.org>2012-03-07 09:58:15 -0800
committerKenneth Graunke <kenneth@whitecape.org>2013-05-09 15:11:53 -0700
commitd0b82b1add5d1d1419d4390a3f7c584b6ee7d92c (patch)
tree82cbc827aac34aea4a3490417fca12138d66f215
parenteca2251f42f0234584d94268c29bddede3ff6451 (diff)
i965: Add chipset limits for the Haswell GT3 variant.
NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 46505537837..5e6e97d4325 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -305,6 +305,12 @@ brwCreateContext(int api,
brw->urb.size = 256;
brw->urb.max_vs_entries = 1664;
brw->urb.max_gs_entries = 640;
+ } else if (intel->gt == 3) {
+ brw->max_wm_threads = 408;
+ brw->max_vs_threads = 280;
+ brw->urb.size = 512;
+ brw->urb.max_vs_entries = 1664;
+ brw->urb.max_gs_entries = 640;
}
} else if (intel->gen == 7) {
if (intel->gt == 1) {