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authorHyunjun Ko <zzoon@igalia.com>2019-11-07 05:28:41 +0000
committerDylan Baker <dylan@pnwbakers.com>2020-02-10 09:01:37 -0800
commitb23a12725834bb1c82387d9883f4e36f7a3d94fd (patch)
tree65eab2985fa996214eb2a3172b0fbf7654196c8b
parent19946a1d2362afa68e685bcea94a3000c2f75079 (diff)
freedreno/ir3: put the conversion back for half const to the right place.
The previous commit leads to match immed values unexpectedly. This makes constlen for each shader including bvert wrong. Also fixes atan2 for mediump deqp tests. Fixes: cbd1f47433b ("freedreno/ir3: convert back to 32-bit values for half constant registers.") v2: Move conversion up above fabs/fneg modifier handling as well. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737> (cherry picked from commit 260bd32b58a55ac0d9870497caef3a4602e19d47)
-rw-r--r--.pick_status.json2
-rw-r--r--src/freedreno/ir3/ir3_cp.c12
2 files changed, 7 insertions, 7 deletions
diff --git a/.pick_status.json b/.pick_status.json
index 285bcb57db3..1d83f3563fe 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -112,7 +112,7 @@
"description": "freedreno/ir3: put the conversion back for half const to the right place.",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"master_sha": null,
"because_sha": "cbd1f47433b7d735e3be5c8126f7f2b9343a1cdf"
},
diff --git a/src/freedreno/ir3/ir3_cp.c b/src/freedreno/ir3/ir3_cp.c
index fa25c9ca8a1..2a0fdf960d4 100644
--- a/src/freedreno/ir3/ir3_cp.c
+++ b/src/freedreno/ir3/ir3_cp.c
@@ -302,6 +302,12 @@ lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags
reg = ir3_reg_clone(ctx->shader, reg);
+ /* Half constant registers seems to handle only 32-bit values
+ * within floating-point opcodes. So convert back to 32-bit values.
+ */
+ if (f_opcode && (new_flags & IR3_REG_HALF))
+ reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
+
/* in some cases, there are restrictions on (abs)/(neg) plus const..
* so just evaluate those and clear the flags:
*/
@@ -347,12 +353,6 @@ lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags
swiz = i % 4;
idx = i / 4;
- /* Half constant registers seems to handle only 32-bit values
- * within floating-point opcodes. So convert back to 32-bit values. */
- if (f_opcode && (new_flags & IR3_REG_HALF)) {
- reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
- }
-
const_state->immediates[idx].val[swiz] = reg->uim_val;
const_state->immediates_count = idx + 1;
const_state->immediate_idx++;