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authorRhys Perry <pendingchaos02@gmail.com>2021-11-12 10:28:24 +0000
committerMarge Bot <emma+marge@anholt.net>2022-04-13 23:08:07 +0000
commit2036a2c5c5ed63439d267b781c01e2edf7c15b74 (patch)
tree30445c5e08579b9666161d8453dbea99230e8c39
parent67fc0e3655550600dcf16e98c78fe368f04b11e9 (diff)
radv: use load_shared2_amd/store_shared2_amd22.1-branchpoint
fossil-db (Sienna Cichlid): Totals from 376 (0.23% of 162293) affected shaders: MaxWaves: 9620 -> 9596 (-0.25%); split: +0.08%, -0.33% Instrs: 207533 -> 203901 (-1.75%); split: -1.76%, +0.01% CodeSize: 1130904 -> 1106420 (-2.16%); split: -2.17%, +0.01% VGPRs: 14016 -> 14120 (+0.74%); split: -0.34%, +1.08% Latency: 2143281 -> 2132212 (-0.52%); split: -0.56%, +0.05% InvThroughput: 389116 -> 387990 (-0.29%); split: -0.34%, +0.05% VClause: 4483 -> 4485 (+0.04%); split: -0.11%, +0.16% SClause: 5780 -> 5778 (-0.03%); split: -0.17%, +0.14% Copies: 15319 -> 15331 (+0.08%); split: -0.53%, +0.61% Branches: 5561 -> 5563 (+0.04%) PreSGPRs: 11776 -> 11775 (-0.01%) PreVGPRs: 11393 -> 11497 (+0.91%); split: -0.13%, +1.04% Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13778>
-rw-r--r--src/amd/vulkan/radv_pipeline.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 7a139f73289..703cb7a3489 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4351,6 +4351,10 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
nir_var_mem_shared | nir_var_mem_global,
.callback = mem_vectorize_callback,
.robust_modes = 0,
+ /* On GFX6, read2/write2 is out-of-bounds if the offset register is negative, even if
+ * the final offset is not.
+ */
+ .has_shared2_amd = device->physical_device->rad_info.chip_class >= GFX7,
};
if (device->robust_buffer_access2) {