summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMarek Olšák <marek.olsak@amd.com>2018-04-13 17:15:06 -0400
committerDylan Baker <dylan@pnwbakers.com>2018-04-30 09:22:08 -0700
commit7d6ed8d0dda59c8d80e140529c77b2f866288c3b (patch)
treebc3a33a436f2ca7f8d1abbea938f02a94292ba85
parent66f64177b298a49591aee18760b8a13a88afa341 (diff)
radeonsi/gfx9: workaround for INTERP with indirect indexing
and clean up the conditions. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 6d19120da851c0d3f97376c733d674f7c8ab0457)
-rw-r--r--src/gallium/drivers/radeonsi/si_get.c19
1 files changed, 13 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index cb28920bbed..04ab0f46bbd 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -477,12 +477,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/* TODO: Indirect indexing of GS inputs is unimplemented. */
- return shader != PIPE_SHADER_GEOMETRY &&
- (sscreen->llvm_has_working_vgpr_indexing ||
- /* TCS and TES load inputs directly from LDS or
- * offchip memory, so indirect indexing is trivial. */
- shader == PIPE_SHADER_TESS_CTRL ||
- shader == PIPE_SHADER_TESS_EVAL);
+ if (shader == PIPE_SHADER_GEOMETRY)
+ return 0;
+
+ if (shader == PIPE_SHADER_VERTEX &&
+ !sscreen->llvm_has_working_vgpr_indexing)
+ return 0;
+
+ /* TCS and TES load inputs directly from LDS or offchip
+ * memory, so indirect indexing is always supported.
+ * PS has to support indirect indexing, because we can't
+ * lower that to TEMPs for INTERP instructions.
+ */
+ return 1;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return sscreen->llvm_has_working_vgpr_indexing ||