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authorJason Ekstrand <jason.ekstrand@intel.com>2018-04-17 15:06:46 -0700
committerJason Ekstrand <jason.ekstrand@intel.com>2018-04-20 16:30:14 -0700
commit185630c6bc973e9a2fec6172325bf31d70bc2eec (patch)
tree4b63707d301c500891b4c03039e1a9877c86a086
parent52e93e309f34972dfd5b84075c13ae8d6b9f63df (diff)
anv/blorp: Do the gen11 BTI flush
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
-rw-r--r--src/intel/vulkan/genX_blorp_exec.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c
index b423046d616..9023269d61b 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -202,6 +202,20 @@ genX(blorp_exec)(struct blorp_batch *batch,
genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
}
+#if GEN_GEN >= 11
+ /* The PIPE_CONTROL command description says:
+ *
+ * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
+ * points to a different RENDER_SURFACE_STATE, SW must issue a Render
+ * Target Cache Flush by enabling this bit. When render target flush
+ * is set due to new association of BTI, PS Scoreboard Stall bit must
+ * be set in this packet."
+ */
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+ ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
+#endif
+
#if GEN_GEN == 7
/* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement
* indirect fast-clear colors can cause GPU hangs if we don't stall first.