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authorJason Ekstrand <jason.ekstrand@intel.com>2017-06-13 10:19:56 -0700
committerAndres Gomez <agomez@igalia.com>2017-06-28 20:15:02 +0300
commitea294dd259f52c8e98714bad535a1848db95f649 (patch)
tree36e235176ca00c57baa851ac71f7589c2013b4e5
parent1161debb608893d4e2116cb9ce85b0237bd23b37 (diff)
i965: Do an end-of-pipe sync prior to STATE_BASE_ADDRESS
Cc: "17.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 96e7b7ac54bd2220905656a0304eed2a753fceee)
-rw-r--r--src/mesa/drivers/dri/i965/brw_misc_state.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index df0a88c5d69..4693f778b5b 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -1009,13 +1009,19 @@ brw_upload_state_base_address(struct brw_context *brw)
* and flushes prior to executing our batch. However, it doesn't seem
* as if the kernel's flushing is always sufficient and we don't want to
* rely on it.
+ *
+ * We make this an end-of-pipe sync instead of a normal flush because we
+ * do not know the current status of the GPU. On Haswell at least,
+ * having a fast-clear operation in flight at the same time as a normal
+ * rendering operation can cause hangs. Since the kernel's flushing is
+ * insufficient, we need to ensure that any rendering operations from
+ * other processes are definitely complete before we try to do our own
+ * rendering. It's a bit of a big hammer but it appears to work.
*/
- brw_emit_pipe_control_flush(brw,
- PIPE_CONTROL_RENDER_TARGET_FLUSH |
- PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- dc_flush |
- PIPE_CONTROL_NO_WRITE |
- PIPE_CONTROL_CS_STALL);
+ brw_emit_end_of_pipe_sync(brw,
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ dc_flush);
}
if (brw->gen >= 8) {