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authorAnuj Phogat <anuj.phogat@gmail.com>2017-06-07 15:47:24 -0700
committerAndres Gomez <agomez@igalia.com>2017-06-28 20:15:05 +0300
commit4c2da8e40dee65e377b29a1d212b096235c6be47 (patch)
treee896812eecd1029081e133d4d73b943fec8f1ed5
parent352263385bea72303a4f2a54ba1ed5c94982fbd0 (diff)
i965: Fix broxton 2x6 l3 config
The new table added in this patch matches with the table in gfxspecs. We were programming the wrong values earlier. V2: Update the comment. Cc: "17.1" <mesa-stable@lists.freedesktop.org> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> (cherry picked from commit 8521559e086a3d56f549962ab8e9f45a6a5989d8) [Andres Gomez: gen 10 was not still there on 17.1] Signed-off-by: Andres Gomez <agomez@igalia.com> Conflicts: src/intel/common/gen_l3_config.c
-rw-r--r--src/intel/common/gen_l3_config.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
index 0783217e676..b67134f1089 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -102,6 +102,20 @@ static const struct gen_l3_config chv_l3_configs[] = {
};
/**
+ * BXT 2x6 validated L3 configurations. \sa ivb_l3_configs.
+ */
+static const struct gen_l3_config bxt_2x6_l3_configs[] = {
+ /* SLM URB ALL DC RO IS C T */
+ {{ 0, 32, 48, 0, 0, 0, 0, 0 }},
+ {{ 0, 32, 0, 8, 40, 0, 0, 0 }},
+ {{ 0, 32, 0, 32, 16, 0, 0, 0 }},
+ {{ 16, 16, 48, 0, 0, 0, 0, 0 }},
+ {{ 16, 16, 0, 40, 8, 0, 0, 0 }},
+ {{ 16, 16, 0, 16, 32, 0, 0, 0 }},
+ {{ 0 }}
+};
+
+/**
* Return a zero-terminated array of validated L3 configurations for the
* specified device.
*/
@@ -116,6 +130,8 @@ get_l3_configs(const struct gen_device_info *devinfo)
return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);
case 9:
+ if (devinfo->l3_banks == 1)
+ return bxt_2x6_l3_configs;
return chv_l3_configs;
default: