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authorJason Ekstrand <jason.ekstrand@intel.com>2017-06-13 10:31:41 -0700
committerAndres Gomez <agomez@igalia.com>2017-06-28 20:15:03 +0300
commit175b0442df3f978b27a86f0fe41dc94b4866a8d3 (patch)
treee6bbe077d8c0b7d39a1cbe65b2402f1b447b8e12
parent7d4dcbcad94ee90d22cd127b7e1c8f17992c47df (diff)
i965: Do an end-of-pipe sync after flushes
According to the docs, a simple CS stall is insufficient to ensure that the memory from the flush is visible and an end-of-pipe sync is needed. Cc: "17.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit d9261275cc1328d6a30e19b92db21df23adf7219)
-rw-r--r--src/mesa/drivers/dri/i965/brw_pipe_control.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index e6909b10ff7..a95892c44cf 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -184,10 +184,10 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
* caches are coherent with memory once the specified R/O caches are
* invalidated. On pre-Gen6 hardware the (implicit) R/O cache
* invalidation seems to happen at the bottom of the pipeline together
- * with any write cache flush, so this shouldn't be a concern.
+ * with any write cache flush, so this shouldn't be a concern. In order
+ * to ensure a full stall, we do an end-of-pipe sync.
*/
- brw_emit_pipe_control_flush(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) |
- PIPE_CONTROL_CS_STALL);
+ brw_emit_end_of_pipe_sync(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS));
flags &= ~(PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_CS_STALL);
}