diff options
| author | Samuel Iglesias Gonsálvez <siglesias@igalia.com> | 2017-02-16 10:47:01 +0100 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2017-03-15 14:39:57 +0000 |
| commit | afa603aedfba85605a6597904e40d4b2032fc069 (patch) | |
| tree | ff9ec6671ee1803ace01cd8d52029440a12d7d59 | |
| parent | 842ea1f3d7ea93b3bf31fbd53c3a2cb4c8c7bc12 (diff) | |
i965/fs: fix source type when emitting MOV_INDIRECT to read ICP handles
When generating the MOV INDIRECT instruction, the source type is ignored
and it is set to destination's type. However, this is going to change in a
later patch, so we need to explicitly set the proper source type.
brw_vec8_grf() creates an float type's fs_reg by default, when the
ICP handle is actually unsigned. This patch fixes these cases before
applying the aforementioned patch.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit d8122128bc6bd291ff0abcb7f2e52d9cdc631527)
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index e445e440286..9c46260c729 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -2005,7 +2005,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst, * we might read up to nir->info.gs.vertices_in registers. */ bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, - fs_reg(brw_vec8_grf(first_icp_handle, 0)), + retype(brw_vec8_grf(first_icp_handle, 0), icp_handle.type), fs_reg(icp_offset_bytes), brw_imm_ud(nir->info.gs.vertices_in * REG_SIZE)); } @@ -2036,7 +2036,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst, * we might read up to ceil(nir->info.gs.vertices_in / 8) registers. */ bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, - fs_reg(brw_vec8_grf(first_icp_handle, 0)), + retype(brw_vec8_grf(first_icp_handle, 0), icp_handle.type), fs_reg(icp_offset_bytes), brw_imm_ud(DIV_ROUND_UP(nir->info.gs.vertices_in, 8) * REG_SIZE)); @@ -2376,7 +2376,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld, /* Start at g1. We might read up to 4 registers. */ bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, - fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes, + retype(brw_vec8_grf(1, 0), icp_handle.type), vertex_offset_bytes, brw_imm_ud(4 * REG_SIZE)); } |