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authorEric Anholt <eric@anholt.net>2015-06-22 11:37:32 -0700
committerEric Anholt <eric@anholt.net>2015-12-11 17:03:03 -0800
commit5ab1bb4becb90649244535ab396b1659a68c0f56 (patch)
tree0fa0cd3aac544748cad3087dd87368be162b2292
parentc5ca18ec2fb1ce5b5bfbe94543e4244815092d76 (diff)
vc4: Rename color_ms_write to color_write.
I was thinking this was the only MSAA resolve thing, so it should be noted separately, but actually load/store general also do MSAA resolve. (cherry picked from commit 568d3a8e32109200cc12549d18118b7660be628b)
-rw-r--r--src/gallium/drivers/vc4/kernel/vc4_render_cl.c29
-rw-r--r--src/gallium/drivers/vc4/vc4_drm.h4
-rw-r--r--src/gallium/drivers/vc4/vc4_job.c10
3 files changed, 21 insertions, 22 deletions
diff --git a/src/gallium/drivers/vc4/kernel/vc4_render_cl.c b/src/gallium/drivers/vc4/kernel/vc4_render_cl.c
index 31784b79771..3447312907b 100644
--- a/src/gallium/drivers/vc4/kernel/vc4_render_cl.c
+++ b/src/gallium/drivers/vc4/kernel/vc4_render_cl.c
@@ -36,7 +36,7 @@
struct vc4_rcl_setup {
struct drm_gem_cma_object *color_read;
- struct drm_gem_cma_object *color_ms_write;
+ struct drm_gem_cma_object *color_write;
struct drm_gem_cma_object *zs_read;
struct drm_gem_cma_object *zs_write;
@@ -146,15 +146,15 @@ static void emit_tile(struct vc4_exec_info *exec,
if (setup->zs_write) {
rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
rcl_u16(setup, args->zs_write.bits |
- (setup->color_ms_write ?
+ (setup->color_write ?
VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR : 0));
rcl_u32(setup,
(setup->zs_write->paddr + args->zs_write.offset) |
- ((last && !setup->color_ms_write) ?
+ ((last && !setup->color_write) ?
VC4_LOADSTORE_TILE_BUFFER_EOF : 0));
}
- if (setup->color_ms_write) {
+ if (setup->color_write) {
if (setup->zs_write) {
/* Reset after previous store */
vc4_tile_coordinates(setup, x, y);
@@ -208,7 +208,7 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
if (setup->zs_write)
loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
- if (setup->color_ms_write) {
+ if (setup->color_write) {
if (setup->zs_write)
loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE;
loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE;
@@ -223,13 +223,12 @@ static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
rcl_u32(setup,
- (setup->color_ms_write ?
- (setup->color_ms_write->paddr +
- args->color_ms_write.offset) :
+ (setup->color_write ? (setup->color_write->paddr +
+ args->color_write.offset) :
0));
rcl_u16(setup, args->width);
rcl_u16(setup, args->height);
- rcl_u16(setup, args->color_ms_write.bits);
+ rcl_u16(setup, args->color_write.bits);
/* The tile buffer gets cleared when the previous tile is stored. If
* the clear values changed between frames, then the tile buffer has
@@ -341,9 +340,9 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
}
static int
-vc4_rcl_ms_surface_setup(struct vc4_exec_info *exec,
- struct drm_gem_cma_object **obj,
- struct drm_vc4_submit_rcl_surface *surf)
+vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
+ struct drm_gem_cma_object **obj,
+ struct drm_vc4_submit_rcl_surface *surf)
{
uint8_t tiling = VC4_GET_FIELD(surf->bits,
VC4_RENDER_CONFIG_MEMORY_FORMAT);
@@ -425,8 +424,8 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
if (ret)
return ret;
- ret = vc4_rcl_ms_surface_setup(exec, &setup.color_ms_write,
- &args->color_ms_write);
+ ret = vc4_rcl_render_config_surface_setup(exec, &setup.color_write,
+ &args->color_write);
if (ret)
return ret;
@@ -441,7 +440,7 @@ int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
/* We shouldn't even have the job submitted to us if there's no
* surface to write out.
*/
- if (!setup.color_ms_write && !setup.zs_write) {
+ if (!setup.color_write && !setup.zs_write) {
DRM_ERROR("RCL requires color or Z/S write\n");
return -EINVAL;
}
diff --git a/src/gallium/drivers/vc4/vc4_drm.h b/src/gallium/drivers/vc4/vc4_drm.h
index 863ef8da8fb..c93454b38fe 100644
--- a/src/gallium/drivers/vc4/vc4_drm.h
+++ b/src/gallium/drivers/vc4/vc4_drm.h
@@ -44,7 +44,7 @@ struct drm_vc4_submit_rcl_surface {
uint32_t hindex; /* Handle index, or ~0 if not present. */
uint32_t offset; /* Offset to start of buffer. */
/*
- * Bits for either render config (color_ms_write) or load/store packet.
+ * Bits for either render config (color_write) or load/store packet.
*/
uint16_t bits;
uint16_t pad;
@@ -126,7 +126,7 @@ struct drm_vc4_submit_cl {
uint8_t max_x_tile;
uint8_t max_y_tile;
struct drm_vc4_submit_rcl_surface color_read;
- struct drm_vc4_submit_rcl_surface color_ms_write;
+ struct drm_vc4_submit_rcl_surface color_write;
struct drm_vc4_submit_rcl_surface zs_read;
struct drm_vc4_submit_rcl_surface zs_write;
uint32_t clear_color[2];
diff --git a/src/gallium/drivers/vc4/vc4_job.c b/src/gallium/drivers/vc4/vc4_job.c
index 9ad79c2ea10..41c2c5fb205 100644
--- a/src/gallium/drivers/vc4/vc4_job.c
+++ b/src/gallium/drivers/vc4/vc4_job.c
@@ -111,9 +111,9 @@ vc4_submit_setup_rcl_surface(struct vc4_context *vc4,
}
static void
-vc4_submit_setup_ms_rcl_surface(struct vc4_context *vc4,
- struct drm_vc4_submit_rcl_surface *submit_surf,
- struct pipe_surface *psurf)
+vc4_submit_setup_rcl_render_config_surface(struct vc4_context *vc4,
+ struct drm_vc4_submit_rcl_surface *submit_surf,
+ struct pipe_surface *psurf)
{
struct vc4_surface *surf = vc4_surface(psurf);
@@ -155,8 +155,8 @@ vc4_job_submit(struct vc4_context *vc4)
vc4_submit_setup_rcl_surface(vc4, &submit.color_read,
vc4->color_read, false, false);
- vc4_submit_setup_ms_rcl_surface(vc4, &submit.color_ms_write,
- vc4->color_write);
+ vc4_submit_setup_rcl_render_config_surface(vc4, &submit.color_write,
+ vc4->color_write);
vc4_submit_setup_rcl_surface(vc4, &submit.zs_read,
vc4->zs_read, true, false);
vc4_submit_setup_rcl_surface(vc4, &submit.zs_write,