diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2015-04-15 03:04:33 -0700 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2015-05-05 14:56:15 +0100 |
| commit | 716b5f7cbe9cb7611d593f170a98facef58e3d0a (patch) | |
| tree | 15f138464adcf4023321e237cde6c46d0d09bc57 | |
| parent | cf60503378f75ef2e9079092a0e6d26a589336dc (diff) | |
i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
The BLT engine on Gen8+ requires linear surfaces to be cacheline
aligned. This restriction was added as part of converting the BLT to
use 48-bit addressing.
intel_emit_linear_blit needs to handle blits that are not cacheline
aligned, as we use it for arbitrary glBufferSubData calls and subrange
mappings.
Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst
pixel X offset field to represent the unaligned portion, and subtract
that from the address so it's cacheline aligned.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1)
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 9500bd70e81..770acf346ba 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -524,6 +524,7 @@ intel_emit_linear_blit(struct brw_context *brw, { struct gl_context *ctx = &brw->ctx; GLuint pitch, height; + int16_t src_x, dst_x; bool ok; /* The pitch given to the GPU must be DWORD aligned, and @@ -532,11 +533,13 @@ intel_emit_linear_blit(struct brw_context *brw, */ pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4); height = (pitch == 0) ? 1 : size / pitch; + src_x = src_offset % 64; + dst_x = dst_offset % 64; ok = intelEmitCopyBlit(brw, 1, - pitch, src_bo, src_offset, I915_TILING_NONE, - pitch, dst_bo, dst_offset, I915_TILING_NONE, - 0, 0, /* src x/y */ - 0, 0, /* dst x/y */ + pitch, src_bo, src_offset - src_x, I915_TILING_NONE, + pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE, + src_x, 0, /* src x/y */ + dst_x, 0, /* dst x/y */ pitch, height, /* w, h */ GL_COPY); if (!ok) @@ -544,15 +547,18 @@ intel_emit_linear_blit(struct brw_context *brw, src_offset += pitch * height; dst_offset += pitch * height; + src_x = src_offset % 64; + dst_x = dst_offset % 64; size -= pitch * height; assert (size < (1 << 15)); pitch = ALIGN(size, 4); + if (size != 0) { ok = intelEmitCopyBlit(brw, 1, - pitch, src_bo, src_offset, I915_TILING_NONE, - pitch, dst_bo, dst_offset, I915_TILING_NONE, - 0, 0, /* src x/y */ - 0, 0, /* dst x/y */ + pitch, src_bo, src_offset - src_x, I915_TILING_NONE, + pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE, + src_x, 0, /* src x/y */ + dst_x, 0, /* dst x/y */ size, 1, /* w, h */ GL_COPY); if (!ok) |