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authorRob Clark <robclark@freedesktop.org>2015-02-21 13:39:06 -0500
committerEmil Velikov <emil.l.velikov@gmail.com>2015-03-12 12:34:50 +0000
commit20ea65beb3ecb45419a45528dc3b7e8bd20bd0e6 (patch)
treeb8b3fdd8ce3db1afd12af2d6d1c507bf2ca79681
parent38777e1345f2471f5889b1f145539e3d5d7a59c7 (diff)
freedreno/a4xx: bit of cleanup
Signed-off-by: Rob Clark <robclark@freedesktop.org> (cherry picked from commit bdf023482a6fd07adef090fb66a4aaaac22810fc)
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_program.c5
-rw-r--r--src/gallium/drivers/freedreno/a4xx/fd4_emit.c6
-rw-r--r--src/gallium/drivers/freedreno/a4xx/fd4_gmem.c7
-rw-r--r--src/gallium/drivers/freedreno/a4xx/fd4_program.c42
4 files changed, 27 insertions, 33 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_program.c b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
index db729434974..b6c448e8650 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_program.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_program.c
@@ -365,7 +365,10 @@ fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit)
COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
OUT_RING(ring, 0x00000000);
} else {
- uint32_t vinterp[4] = {0}, flatshade[2] = {0};
+ uint32_t vinterp[4], flatshade[2];
+
+ memset(vinterp, 0, sizeof(vinterp));
+ memset(flatshade, 0, sizeof(flatshade));
/* figure out VARYING_INTERP / FLAT_SHAD register values: */
for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 037f4550587..1d098f2701f 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -425,13 +425,9 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
- }
- if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
- uint32_t val = fd4_rasterizer_stateobj(ctx->rasterizer)
- ->gras_cl_clip_cntl;
OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
- OUT_RING(ring, val);
+ OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
}
/* NOTE: since primitive_restart is not actually part of any
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
index f4ab9103c81..c52fa997191 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
@@ -436,13 +436,6 @@ fd4_emit_sysmem_prep(struct fd_context *ctx)
{
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
struct fd_ringbuffer *ring = ctx->ring;
- uint32_t pitch = 0;
-
- if (pfb->cbufs[0]) {
- struct pipe_surface *psurf = pfb->cbufs[0];
- unsigned lvl = psurf->u.tex.level;
- pitch = fd_resource(psurf->texture)->slices[lvl].pitch;
- }
fd4_emit_restore(ctx);
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_program.c b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
index cbfd8b2d4cc..776e4a16b14 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_program.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
@@ -420,8 +420,28 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit)
COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
OUT_RING(ring, 0x00000000);
} else {
- uint32_t vinterp[8] = {0}, flatshade[2] = {0};
+ uint32_t vinterp[8], flatshade[2];
+ memset(vinterp, 0, sizeof(vinterp));
+ memset(flatshade, 0, sizeof(flatshade));
+
+ /* TODO: looks like we need to do int varyings in the frag
+ * shader on a4xx (no flatshad reg?):
+ *
+ * (sy)(ss)nop
+ * (sy)ldlv.u32 r0.x,l[r0.x], 1
+ * ldlv.u32 r0.y,l[r0.x+1], 1
+ * (ss)bary.f (ei)r63.x, 0, r0.x
+ * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
+ * (rpt5)nop
+ * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
+ *
+ * for now, don't set FLAT on vinterp[], since that
+ * at least works well enough for pure float impl (ie.
+ * pre glsl130).. we'll have to do a bit more work to
+ * handle this properly:
+ */
+#if 0
/* figure out VARYING_INTERP / FLAT_SHAD register values: */
for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
uint32_t interp = s[FS].v->inputs[j].interpolate;
@@ -443,25 +463,7 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit)
}
}
}
-
- /* HACK: looks like we need to do int varyings in the frag
- * shader on a4xx (no flatshad reg?):
- *
- * (sy)(ss)nop
- * (sy)ldlv.u32 r0.x,l[r0.x], 1
- * ldlv.u32 r0.y,l[r0.x+1], 1
- * (ss)bary.f (ei)r63.x, 0, r0.x
- * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
- * (rpt5)nop
- * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
- *
- * for now, don't set FLAT on vinterp[], since that
- * at least works well enough for pure float impl (ie.
- * pre glsl130).. we'll have to do a bit more work to
- * handle this properly:
- */
- for (i = 0; i < ARRAY_SIZE(vinterp); i++)
- vinterp[i] = 0;
+#endif
OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |