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authorBen Widawsky <benjamin.widawsky@intel.com>2014-12-04 15:37:17 -0800
committerEmil Velikov <emil.l.velikov@gmail.com>2014-12-11 13:17:45 +0000
commitdd5ffb2d3168ef3b05122424856a32449d16be1e (patch)
tree3e458659191aec65f42f9e1f4db506b84a4e7eb0
parent103fadef9d0290fd90fce2200a75643cb244cd8e (diff)
i965/gs: Avoid DW * DW mul
The GS has an interesting use for mul. Because the GS can emit multiple vertices per input vertex, and it also has a unique count at the top of the URB payload, the GS unit needs to be able to dynamically specify URB write offsets (relative to the global offset). The documentation in the function has a very good explanation from Paul on the mechanics. This fixes around 2000 piglit tests on BSW. v2: Reworded commit message (Ben) no mention of CHV (Matt) Change SHRT_MAX to USHRT_MAX (Ken, and Matt) Update comment in code to reflect the use of UW (Ben) Add Gen7+ assertion for the relevant GS code, since it won't work on Gen6- (Ken) Drop the bogus hunk in emit_control_data_bits() (Ken) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84777 (with many dupes) Cc: "10.4 10.3 10.2" <mesa-stable@lists.freedesktop.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit f13870db09d7a10141b5ffc24058bb2abceaa035)
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_generator.cpp8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index a5c2d1a2f8c..3dc7d6ba412 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -502,13 +502,17 @@ vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
*
* We can do this with the following EU instruction:
*
- * mul(2) dst.3<1>UD src0<8;2,4>UD src1 { Align1 WE_all }
+ * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
*/
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+ assert(brw->gen >= 7 &&
+ src1.file == BRW_IMMEDIATE_VALUE &&
+ src1.type == BRW_REGISTER_TYPE_UD &&
+ src1.dw1.ud <= USHRT_MAX);
brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
- src1);
+ retype(src1, BRW_REGISTER_TYPE_UW));
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_pop_insn_state(p);
}