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authorMarek Olšák <marek.olsak@amd.com>2014-10-22 23:22:16 +0200
committerEmil Velikov <emil.l.velikov@gmail.com>2014-10-29 18:17:36 +0000
commite8c7affa66407932519fc6d82a449b453343d9fc (patch)
tree2b5b61b7cd50e32d14e48d5792151f7adcbd129e
parent62b2c8aca0a19c77ce6ac58c4721e37d37cb8c40 (diff)
radeonsi: fix incorrect index buffer max size for lowered 8-bit indices
Cc: 10.2 10.3 mesa-stable@lists.freedesktop.org Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (cherry picked from commit e05259b63745533231d7094967e7e1066a0e0851)
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 0f700a8c9eb..cdc350c9d8f 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -781,7 +781,7 @@ static void si_state_draw(struct si_context *sctx,
if (info->indexed) {
uint32_t max_size = (ib->buffer->width0 - ib->offset) /
- sctx->index_buffer.index_size;
+ ib->index_size;
uint64_t va = r600_resource(ib->buffer)->gpu_address + ib->offset;
si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,