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authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>2021-05-04 23:34:42 +0000
committerMarge Bot <eric+marge@anholt.net>2021-05-05 11:05:19 +0000
commitc05e48308b432f93785520f48fbddc813040b11d (patch)
tree0f85a2552c875fff01e2ea79b034ad699760aec9
parentd8ab0ec8e4d23c534fe5a9c54941490a26977800 (diff)
radeon/vcn: Use the correct pitch for chroma surface.
The pitch of the chroma plane isn't necessarily half that of the luma plane, as tiling (and presumably even linear) swizzle modes apply some alignment. Fixes: 35e25ea1d07 ("ac/surface: allow non-DCC modifiers for YUV on GFX9+") Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10638>
-rw-r--r--src/gallium/drivers/radeon/radeon_vcn_dec.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 310eb9aadf6..569f57d4e57 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1649,7 +1649,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->db_surf_tile_config = 0;
decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
- decode->dt_uv_pitch = decode->dt_pitch / 2;
+ decode->dt_uv_pitch = chroma->surface.u.gfx9.surf_pitch * chroma->surface.blk_w;
if (luma->surface.meta_offset) {
RVID_ERR("DCC surfaces not supported.\n");
@@ -1675,7 +1675,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->dt_chroma_bottom_offset = decode->dt_chroma_top_offset;
}
if (dec->stream_type == RDECODE_CODEC_AV1)
- decode->db_pitch_uv = decode->db_pitch / 2;
+ decode->db_pitch_uv = chroma->surface.u.gfx9.surf_pitch * chroma->surface.blk_w;
if (encrypted) {
assert(sscreen->info.has_tmz_support);