diff options
author | Marek Olšák <marek.olsak@amd.com> | 2022-05-26 11:55:08 -0400 |
---|---|---|
committer | Dylan Baker <dylan.c.baker@intel.com> | 2022-06-08 10:58:17 -0700 |
commit | 2a835a2da3cda81e23321d755712485fa8b55816 (patch) | |
tree | f071b46c15d78a18006807b9e6eedc5d2fa1b45a | |
parent | dc28a8fd88f561d88e331cdc173f9f4372def24d (diff) |
ac/gpu_info: always retile DCC on gfx10 and newer chips
Unaligned DCC doesn't work there.
Fixes: f8cf5ea982a - amd: add support for gfx1036 and gfx1037 chips
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16726>
-rw-r--r-- | .pick_status.json | 2 | ||||
-rw-r--r-- | src/amd/common/ac_gpu_info.c | 3 | ||||
-rw-r--r-- | src/amd/common/ac_surface.c | 13 |
3 files changed, 3 insertions, 15 deletions
diff --git a/.pick_status.json b/.pick_status.json index 02cb5d7582f..d24937c0985 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -4783,7 +4783,7 @@ "description": "ac/gpu_info: always retile DCC on gfx10 and newer chips", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 3, "main_sha": null, "because_sha": "f8cf5ea982adc4e1d5b6a531f83eea938583c830" }, diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index c63c392c0b9..f320ccc18c5 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1173,7 +1173,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, if ((info->drm_minor >= 31 && (info->family == CHIP_RAVEN || info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR)) || info->chip_class >= GFX10_3) { - if (info->max_render_backends == 1) + /* GFX10+ requires retiling in all cases. */ + if (info->max_render_backends == 1 && info->chip_class == GFX9) info->use_display_dcc_unaligned = true; else info->use_display_dcc_with_retile_blit = true; diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 58348a02698..f07c465220c 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -355,12 +355,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) if (info->chip_class >= GFX10_3) { - if (info->max_render_backends == 1) { - ADD_MOD(AMD_FMT_MOD | common_dcc | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) - } - ADD_MOD(AMD_FMT_MOD | common_dcc | AMD_FMT_MOD_SET(DCC_RETILE, 1) | AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | @@ -370,13 +364,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14 || info->chip_class >= GFX10_3) { bool independent_128b = info->chip_class >= GFX10_3; - if (info->max_render_backends == 1) { - ADD_MOD(AMD_FMT_MOD | common_dcc | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, independent_128b) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)) - } - ADD_MOD(AMD_FMT_MOD | common_dcc | AMD_FMT_MOD_SET(DCC_RETILE, 1) | AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | |