diff options
| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2021-01-25 13:42:35 +0100 |
|---|---|---|
| committer | Marge Bot <eric+marge@anholt.net> | 2021-03-17 19:14:29 +0000 |
| commit | 6f104e9ac821b8d15d21261d2f29939ed639e73e (patch) | |
| tree | 13f34e8e4b42a162ee7bb056b6da86f0ddf89741 | |
| parent | 713b589d3410a9d692d28e194e7b09fd6b791c84 (diff) | |
radv,aco: fix shifting input VGPRs for the LS VGPR init bug on GFX9
We were incorrectly shifting the input VGPRs for the instance ID
for chips affected by the LS VGPR init bug (ie. Vega10 and Raven).
When there is no HS threads, the hardware loads the LS VGPR
starting from VGPR 0, so they should be shifted by two.
This fixes some sort of vertex explosion with Squad, Visage, Barn
Finders and probably more titles that use tessellation. Note that
only Vega10 and Raven were affected by this bug.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4129
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3311
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Diego Viola <diego.viola@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9557>
| -rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 2 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_nir_to_llvm.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 628ca28fd4b..2cc1e2c2cfa 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -10936,7 +10936,7 @@ void fix_ls_vgpr_init_bug(isel_context *ctx, Pseudo_instruction *startpgm) /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */ Temp instance_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), - get_arg(ctx, ctx->args->rel_auto_id), + get_arg(ctx, ctx->args->ac.vertex_id), get_arg(ctx, ctx->args->ac.instance_id), ls_has_nonzero_hs_threads); Temp rel_auto_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index b591c969d2d..f38d36c5a69 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -3758,7 +3758,7 @@ static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx) LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count, ctx->ac.i32_0, ""); ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, - ac_get_arg(&ctx->ac, ctx->args->rel_auto_id), + ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id), ctx->abi.instance_id, ""); ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids), |