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authorCaio Marcelo de Oliveira Filho <caio.oliveira@intel.com>2020-01-31 10:20:25 -0800
committerDylan Baker <dylan@pnwbakers.com>2020-02-20 13:36:32 -0800
commit6d93c67532338f184ba60d6ae1d2dee7c5b338f0 (patch)
treebc833ede5ad13a7443f95048206490deafe6a89a
parenta2c51d909cd6e7ff142a314efe8be78cfb34f536 (diff)
intel/gen12: Take into account opcode when decoding SWSB
The interpretation of the fields is different depending whether the instruction is a SEND/MATH or not. This fixes the disassembly output for non-SEND/MATH instructions that have both in-order and out-of-order dependencies. Their dependencies were wrongly represented as `@A $B` when the correct would be `@A $B.dst`. Fixes: 6154cdf924f ("intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.") Fixes: 83612c01271 ("intel/disasm/gen12: Disassemble software scoreboard information.") Acked-by: Francisco Jerez <currojerez@riseup.net> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3660> (cherry picked from commit 79788b8f7f07460af8467931501380e47b485e36)
-rw-r--r--.pick_status.json2
-rw-r--r--src/intel/compiler/brw_disasm.c3
-rw-r--r--src/intel/compiler/brw_eu_defines.h7
3 files changed, 8 insertions, 4 deletions
diff --git a/.pick_status.json b/.pick_status.json
index 3021aa052d8..3f176a18ba9 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -517,7 +517,7 @@
"description": "intel/gen12: Take into account opcode when decoding SWSB",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"master_sha": null,
"because_sha": "6154cdf924f4d0d3a6fb0cef38bc62eb4494c69c"
},
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 7d821dbc1fa..d0960dbb181 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1607,7 +1607,8 @@ qtr_ctrl(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst
static int
swsb(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
{
- const struct tgl_swsb swsb = tgl_swsb_decode(brw_inst_swsb(devinfo, inst));
+ const struct tgl_swsb swsb = tgl_swsb_decode(brw_inst_opcode(devinfo, inst),
+ brw_inst_swsb(devinfo, inst));
if (swsb.regdist)
format(file, " @%d", swsb.regdist);
if (swsb.mode)
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 8aa2c14fddf..737ea95215b 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -1135,11 +1135,14 @@ tgl_swsb_encode(struct tgl_swsb swsb)
* tgl_swsb.
*/
static inline struct tgl_swsb
-tgl_swsb_decode(uint8_t x)
+tgl_swsb_decode(enum opcode opcode, uint8_t x)
{
if (x & 0x80) {
const struct tgl_swsb swsb = { (x & 0x70u) >> 4, x & 0xfu,
- TGL_SBID_DST | TGL_SBID_SET };
+ (opcode == BRW_OPCODE_SEND ||
+ opcode == BRW_OPCODE_SENDC ||
+ opcode == BRW_OPCODE_MATH) ?
+ TGL_SBID_SET : TGL_SBID_DST };
return swsb;
} else if ((x & 0x70) == 0x20) {
return tgl_swsb_sbid(TGL_SBID_DST, x & 0xfu);