diff options
| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2018-03-23 09:27:55 -0700 |
|---|---|---|
| committer | Juan A. Suarez Romero <jasuarez@igalia.com> | 2018-04-11 18:50:24 +0200 |
| commit | 542951a9f020f57c538f0f07db5905cb0ced8375 (patch) | |
| tree | 523ca6b91f71cac6263d2a225c3bb2e9fee97de3 | |
| parent | 51b4bdc7761b30a56299ee80f51521151d4eec47 (diff) | |
intel/vec4: Set channel_sizes for MOV_INDIRECT sources
Otherwise, any indirect push constant access results in an assertion
failure when we start digging through the channel_sizes array. This
fixes dEQP-VK.pipeline.push_constant.graphics_pipeline.dynamic_index_vert
on Haswell. It should be a harmless no-op for GL since indirect push
constants aren't used there.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Fixes: e69e5c7006d "i965/vec4: load dvec3/4 uniforms first in the..."
(cherry picked from commit 2b977989f3f01c186677988494bbf9b7342b31f2)
| -rw-r--r-- | src/intel/compiler/brw_vec4.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index 0c22dcbde52..03a613689e8 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -688,8 +688,11 @@ vec4_visitor::pack_uniform_registers() * the next part of our packing algorithm. */ int reg = inst->src[0].nr; - for (unsigned i = 0; i < vec4s_read; i++) + int channel_size = type_sz(inst->src[0].type) / 4; + for (unsigned i = 0; i < vec4s_read; i++) { chans_used[reg + i] = 4; + channel_sizes[reg + i] = MAX2(channel_sizes[reg + i], channel_size); + } } } |