i965: Fix clear code for ignoring colormask for XRGB formats on Gen9+.

In commit cda886a4851ab767fba40e8474d6fa8190347e4f, Neil made us stop
advertising RGBX formats on Gen9+, as the hardware apparently no longer
has working fast clear support for those formats.  Instead, we just
fall back to RGBA formats, and use SCS to override alpha to 1.0.

This is fine, but had one unintended side effect: it made us fall back
to slow clears when the color mask disables alpha.  Normally, we ignore
the color mask for non-existent channels.  This includes alpha for XRGB
formats as writing garbage to the X channel is harmless.  But, now that
we use RGBA, we think there's a real alpha channel, and can't do the
optimization.

To hack around this, check if _BaseFormat is GL_RGB and ignore alpha.

Improves WebGL Aquarium performance on Skylake GT3e by about 50%
by letting it use repclears instead of slow clears.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
(cherry picked from commit 73b01e2711ff45a1f313d5372d6c8fa4fe55d4d2)

1 files changed, 1 insertions, 0 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 488fa6c0c45..cedaf4407e8 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -651,6 +651,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
       GLubyte *color_mask = ctx->Color.ColorMask[buf];
       for (int i = 0; i < 4; i++) {
          if (_mesa_format_has_color_component(irb->mt->format, i) &&
+             !(i == 3 && irb->Base.Base._BaseFormat == GL_RGB) &&
              !color_mask[i]) {
             perf_debug("Falling back to plain clear on %dx%d buffer because of color mask\n",
                        irb->mt->logical_width0, irb->mt->logical_height0);