diff options
| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2015-10-09 18:07:23 -0700 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2016-05-05 13:59:32 +0100 |
| commit | 8d1874bc1cd2d2e479cbefb35f4d22d9dd378178 (patch) | |
| tree | cd6fb81e5adf12e27b4bb0de03195eb2cd29ebde | |
| parent | 143161ad97581388b6a34037a2bfd697098868e8 (diff) | |
i965/fs: Properly report regs_written from SAMPLEINFO
The previous behavior would only allocate one register and then write
four thus potentially stomping three innocent bystanders.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
(cherry picked from commit c7a09c057162ed0b7e9e039470c76bb79518876c)
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_shader.cpp | 3 |
2 files changed, 9 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index db20c71406e..309b10d4e01 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -3060,12 +3060,18 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr) case nir_texop_txs: op = ir_txs; break; case nir_texop_texture_samples: { fs_reg dst = retype(get_nir_dest(instr->dest), BRW_REGISTER_TYPE_D); - fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, dst, + + fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D, 4); + fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, tmp, bld.vgrf(BRW_REGISTER_TYPE_D, 1), texture_reg, texture_reg); inst->mlen = 1; inst->header_size = 1; inst->base_mrf = -1; + inst->regs_written = 4 * (dispatch_width / 8); + + /* Pick off the one component we care about */ + bld.MOV(dst, tmp); return; } case nir_texop_samples_identical: op = ir_samples_identical; break; diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 91e47800e1f..70a7f443fe8 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -710,7 +710,8 @@ backend_instruction::is_tex() const opcode == SHADER_OPCODE_TXS || opcode == SHADER_OPCODE_LOD || opcode == SHADER_OPCODE_TG4 || - opcode == SHADER_OPCODE_TG4_OFFSET); + opcode == SHADER_OPCODE_TG4_OFFSET || + opcode == SHADER_OPCODE_SAMPLEINFO); } bool |