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authorOded Gabbay <oded.gabbay@gmail.com>2016-03-21 23:46:15 +0200
committerEmil Velikov <emil.l.velikov@gmail.com>2016-05-05 11:47:20 +0100
commit3f40f8e4f28f05bb2220c8356227b98a921efe9b (patch)
tree450d6f5b5066493a3d36f29a9bf51b43a00f461a
parentf64bcc7f7d3b68e7752a90d9d55d1dc481608175 (diff)
r600g/radeonsi: send endian info to format translation functions
Because r600 GPUs can't do swap in their DB unit, we need to disable endianess swapping for textures that are handled by DB. There are four format translation functions in r600g driver: - r600_translate_texformat - r600_colorformat_endian_swap - r600_translate_colorformat - r600_translate_colorswap This patch adds a new parameters to those functions, called "do_endian_swap". When running in a big-endian machine, the calling functions will check whether the texture/color is handled by DB - "rtex->is_depth && !rtex->is_flushing_texture" - and if so, they will send FALSE through this parameter. Otherwise, they will send TRUE. The translation functions, in specific cases, will look at this parameter and configure the swapping accordingly. v4: evergreen_init_color_surface_rat() is only used by compute and don't handle DB surfaces, so just sent hard-coded FALSE to translation functions when called by it. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 2242dbe11d56b05ede7a928a9973adda4b145ad7) Squashed with commit radeonsi: fix build error because of missing param Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com> Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 514c5b5f4b692e2596341e08797c4f6dc8cdfe00) [Emil Velikov: resolve trivial conflicts] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Conflicts: src/gallium/drivers/radeonsi/si_state.c
-rw-r--r--src/gallium/drivers/r600/evergreen_state.c33
-rw-r--r--src/gallium/drivers/r600/r600_pipe.h8
-rw-r--r--src/gallium/drivers/r600/r600_state.c27
-rw-r--r--src/gallium/drivers/r600/r600_state_common.c8
-rw-r--r--src/gallium/drivers/radeon/r600_pipe_common.h2
-rw-r--r--src/gallium/drivers/radeon/r600_texture.c4
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c6
7 files changed, 55 insertions, 33 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index cf3fa99570f..e50f493e54c 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -213,13 +213,14 @@ static uint32_t r600_translate_dbformat(enum pipe_format format)
static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
{
- return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
+ return r600_translate_texformat(screen, format, NULL, NULL, NULL,
+ FALSE) != ~0U;
}
static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
{
- return r600_translate_colorformat(chip, format) != ~0U &&
- r600_translate_colorswap(format) != ~0U;
+ return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
+ r600_translate_colorswap(format, FALSE) != ~0U;
}
static bool r600_is_zs_format_supported(enum pipe_format format)
@@ -668,6 +669,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
unsigned base_level, first_level, last_level;
unsigned dim, last_layer;
uint64_t va;
+ bool do_endian_swap = FALSE;
if (view == NULL)
return NULL;
@@ -713,16 +715,19 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
}
}
+ if (R600_BIG_ENDIAN)
+ do_endian_swap = !(tmp->is_depth && !tmp->is_flushing_texture);
+
format = r600_translate_texformat(ctx->screen, pipe_format,
swizzle,
- &word4, &yuv_format);
+ &word4, &yuv_format, do_endian_swap);
assert(format != ~0);
if (format == ~0) {
FREE(view);
return NULL;
}
- endian = r600_colorformat_endian_swap(format);
+ endian = r600_colorformat_endian_swap(format, do_endian_swap);
base_level = 0;
first_level = state->u.tex.first_level;
@@ -953,9 +958,9 @@ void evergreen_init_color_surface_rat(struct r600_context *rctx,
{
struct pipe_resource *pipe_buffer = surf->base.texture;
unsigned format = r600_translate_colorformat(rctx->b.chip_class,
- surf->base.format);
- unsigned endian = r600_colorformat_endian_swap(format);
- unsigned swap = r600_translate_colorswap(surf->base.format);
+ surf->base.format, FALSE);
+ unsigned endian = r600_colorformat_endian_swap(format, FALSE);
+ unsigned swap = r600_translate_colorswap(surf->base.format, FALSE);
unsigned block_size =
align(util_format_get_blocksize(pipe_buffer->format), 4);
unsigned pitch_alignment =
@@ -1008,7 +1013,7 @@ void evergreen_init_color_surface(struct r600_context *rctx,
unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
const struct util_format_description *desc;
int i;
- bool blend_clamp = 0, blend_bypass = 0;
+ bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
offset = rtex->surface.level[level].offset;
if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
@@ -1106,13 +1111,17 @@ void evergreen_init_color_surface(struct r600_context *rctx,
ntype = V_028C70_NUMBER_UINT;
}
- format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
+ if (R600_BIG_ENDIAN)
+ do_endian_swap = !(rtex->is_depth && !rtex->is_flushing_texture);
+
+ format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
+ do_endian_swap);
assert(format != ~0);
- swap = r600_translate_colorswap(surf->base.format);
+ swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
assert(swap != ~0);
- endian = r600_colorformat_endian_swap(format);
+ endian = r600_colorformat_endian_swap(format, do_endian_swap);
/* blend clamp should be set for all NORM/SRGB types */
if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index c8ee612658e..86af9b82e54 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -722,9 +722,11 @@ unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
boolean vtx);
uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
const unsigned char *swizzle_view,
- uint32_t *word4_p, uint32_t *yuv_format_p);
-uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format);
-uint32_t r600_colorformat_endian_swap(uint32_t colorformat);
+ uint32_t *word4_p, uint32_t *yuv_format_p,
+ bool do_endian_swap);
+uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
+ bool do_endian_swap);
+uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap);
/* r600_uvd.c */
struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context,
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 5b59af4787f..6131d1e8dcd 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -143,13 +143,14 @@ static uint32_t r600_translate_dbformat(enum pipe_format format)
static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
{
- return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
+ return r600_translate_texformat(screen, format, NULL, NULL, NULL,
+ FALSE) != ~0U;
}
static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format)
{
- return r600_translate_colorformat(chip, format) != ~0U &&
- r600_translate_colorswap(format) != ~0U;
+ return r600_translate_colorformat(chip, format, FALSE) != ~0U &&
+ r600_translate_colorswap(format, FALSE) != ~0U;
}
static bool r600_is_zs_format_supported(enum pipe_format format)
@@ -641,6 +642,7 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
uint32_t word4 = 0, yuv_format = 0, pitch = 0;
unsigned char swizzle[4], array_mode = 0;
unsigned width, height, depth, offset_level, last_level;
+ bool do_endian_swap = FALSE;
if (view == NULL)
return NULL;
@@ -661,9 +663,12 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
swizzle[2] = state->swizzle_b;
swizzle[3] = state->swizzle_a;
+ if (R600_BIG_ENDIAN)
+ do_endian_swap = !(tmp->is_depth && !tmp->is_flushing_texture);
+
format = r600_translate_texformat(ctx->screen, state->format,
swizzle,
- &word4, &yuv_format);
+ &word4, &yuv_format, do_endian_swap);
assert(format != ~0);
if (format == ~0) {
FREE(view);
@@ -678,7 +683,7 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
tmp = tmp->flushed_depth_texture;
}
- endian = r600_colorformat_endian_swap(format);
+ endian = r600_colorformat_endian_swap(format, do_endian_swap);
offset_level = state->u.tex.first_level;
last_level = state->u.tex.last_level - offset_level;
@@ -861,7 +866,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
unsigned offset;
const struct util_format_description *desc;
int i;
- bool blend_bypass = 0, blend_clamp = 1;
+ bool blend_bypass = 0, blend_clamp = 1, do_endian_swap = FALSE;
if (rtex->is_depth && !rtex->is_flushing_texture && !r600_can_read_depth(rtex)) {
r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
@@ -924,13 +929,17 @@ static void r600_init_color_surface(struct r600_context *rctx,
ntype = V_0280A0_NUMBER_UINT;
}
- format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format);
+ if (R600_BIG_ENDIAN)
+ do_endian_swap = !(rtex->is_depth && !rtex->is_flushing_texture);
+
+ format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format,
+ do_endian_swap);
assert(format != ~0);
- swap = r600_translate_colorswap(surf->base.format);
+ swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
assert(swap != ~0);
- endian = r600_colorformat_endian_swap(format);
+ endian = r600_colorformat_endian_swap(format, do_endian_swap);
/* set blend bypass according to docs if SINT/UINT or
8/24 COLOR variants */
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 40cf38ed502..bd34eddf1b6 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -2025,7 +2025,8 @@ unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
uint32_t r600_translate_texformat(struct pipe_screen *screen,
enum pipe_format format,
const unsigned char *swizzle_view,
- uint32_t *word4_p, uint32_t *yuv_format_p)
+ uint32_t *word4_p, uint32_t *yuv_format_p,
+ bool do_endian_swap)
{
struct r600_screen *rscreen = (struct r600_screen *)screen;
uint32_t result = 0, word4 = 0, yuv_format = 0;
@@ -2398,7 +2399,8 @@ out_unknown:
return ~0;
}
-uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format)
+uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format,
+ bool do_endian_swap)
{
const struct util_format_description *desc = util_format_description(format);
int channel = util_format_get_first_non_void_channel(format);
@@ -2498,7 +2500,7 @@ uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format forma
return ~0U;
}
-uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
+uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
{
if (R600_BIG_ENDIAN) {
switch(colorformat) {
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index bcf0871e707..7636d373027 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -546,7 +546,7 @@ struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_surface *templ,
unsigned width, unsigned height);
-unsigned r600_translate_colorswap(enum pipe_format format);
+unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
struct pipe_framebuffer_state *fb,
struct r600_atom *fb_state,
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 28aca5db8ca..e1d7cd44e31 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1182,7 +1182,7 @@ static void r600_surface_destroy(struct pipe_context *pipe,
FREE(surface);
}
-unsigned r600_translate_colorswap(enum pipe_format format)
+unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap)
{
const struct util_format_description *desc = util_format_description(format);
@@ -1281,7 +1281,7 @@ static void vi_get_fast_clear_parameters(enum pipe_format surface_format,
surface_format == PIPE_FORMAT_B5G6R5_SRGB) {
extra_channel = -1;
} else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
- if(r600_translate_colorswap(surface_format) <= 1)
+ if(r600_translate_colorswap(surface_format, FALSE) <= 1)
extra_channel = desc->nr_channels - 1;
else
extra_channel = 0;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 616a05b4cd9..298a30068a0 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1694,7 +1694,7 @@ static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_
static bool si_is_colorbuffer_format_supported(enum pipe_format format)
{
return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
- r600_translate_colorswap(format) != ~0U;
+ r600_translate_colorswap(format, FALSE) != ~0U;
}
static bool si_is_zs_format_supported(enum pipe_format format)
@@ -1861,7 +1861,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
}
assert(format != V_028C70_COLOR_INVALID);
- swap = r600_translate_colorswap(surf->base.format);
+ swap = r600_translate_colorswap(surf->base.format, FALSE);
endian = si_colorformat_endian_swap(format);
/* blend clamp should be set for all NORM/SRGB types */
@@ -2653,7 +2653,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
if (tmp->dcc_buffer) {
uint64_t dcc_offset = surflevel[base_level].dcc_offset;
- unsigned swap = r600_translate_colorswap(pipe_format);
+ unsigned swap = r600_translate_colorswap(pipe_format, FALSE);
view->state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
view->state[7] = (tmp->dcc_buffer->gpu_address + dcc_offset) >> 8;