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| author | Matt Turner <mattst88@gmail.com> | 2015-05-14 15:58:20 -0700 |
|---|---|---|
| committer | Matt Turner <mattst88@gmail.com> | 2015-05-18 10:11:36 -0700 |
| commit | 0a9e3a0160bbda8ea23aeb049f9c3dfc0478bbf5 (patch) | |
| tree | 1f5d8b77ac9e6a9eb81ea7e4c5a2e0e50e32e252 | |
| parent | 4ec09c77471e39e6ff81c99f1edde2e1713a7f24 (diff) | |
i965/fs: Rework compression control selection.
The next commit uses an add(16) with a UW destination with a stride of
2, which needs compression control since it's writing two registers. The
old code would have failed to set compression control correctly.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index b6b0d0523a0..0be0f866558 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1601,10 +1601,13 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) break; case 16: case 32: - if (type_sz(inst->dst.type) < sizeof(float)) - brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); - else + /* If the instruction writes to more than one register, it needs to + * be a "compressed" instruction on Gen <= 5. + */ + if (inst->exec_size * inst->dst.stride * type_sz(inst->dst.type) > 32) brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED); + else + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); break; default: unreachable("Invalid instruction width"); |