diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2014-05-08 16:44:37 -0700 |
|---|---|---|
| committer | Ian Romanick <ian.d.romanick@intel.com> | 2014-05-09 20:10:37 -0700 |
| commit | ec6bd2116253045764d51998d883b2471d53ab51 (patch) | |
| tree | bbc76add3d9a18bcf8e2e87e72593a1e4bfe24a3 | |
| parent | 53a0f9d0ba8a0593abbc0c2a0ca03399aac2bb53 (diff) | |
i965: Fix GPU hangs on Broadwell in shaders with some control flow.
According to the documentation, we need to set the source 0 register
type to IMM for flow control instructions that have both JIP and UIP.
Fixes GPU hangs in approximately 10 Piglit tests, 5 es3conform tests,
Unigine Crypt, a WebGL raytracer demo, and several Steam titles.
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75478
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75878
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76939
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Tested-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 9584959123b0453cf5313722357e3abb9f736aa7)
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_generator.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_generator.cpp b/src/mesa/drivers/dri/i965/gen8_generator.cpp index dd434a75544..faca9c08835 100644 --- a/src/mesa/drivers/dri/i965/gen8_generator.cpp +++ b/src/mesa/drivers/dri/i965/gen8_generator.cpp @@ -422,6 +422,7 @@ gen8_generator::IF(unsigned predicate) { gen8_instruction *inst = next_inst(BRW_OPCODE_IF); gen8_set_dst(brw, inst, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D))); + gen8_set_src0(brw, inst, brw_imm_d(0)); gen8_set_exec_size(inst, default_state.exec_size); gen8_set_pred_control(inst, predicate); gen8_set_mask_control(inst, BRW_MASK_ENABLE); @@ -435,6 +436,7 @@ gen8_generator::ELSE() { gen8_instruction *inst = next_inst(BRW_OPCODE_ELSE); gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + gen8_set_src0(brw, inst, brw_imm_d(0)); gen8_set_mask_control(inst, BRW_MASK_ENABLE); push_if_stack(inst); return inst; @@ -456,6 +458,7 @@ gen8_generator::ENDIF() gen8_instruction *endif_inst = next_inst(BRW_OPCODE_ENDIF); gen8_set_mask_control(endif_inst, BRW_MASK_ENABLE); + gen8_set_src0(brw, endif_inst, brw_imm_d(0)); patch_IF_ELSE(if_inst, else_inst, endif_inst); return endif_inst; @@ -577,8 +580,7 @@ gen8_generator::BREAK() { gen8_instruction *inst = next_inst(BRW_OPCODE_BREAK); gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - gen8_set_src0(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - gen8_set_src1(brw, inst, brw_imm_d(0)); + gen8_set_src0(brw, inst, brw_imm_d(0)); gen8_set_exec_size(inst, default_state.exec_size); return inst; } @@ -588,8 +590,7 @@ gen8_generator::CONTINUE() { gen8_instruction *inst = next_inst(BRW_OPCODE_CONTINUE); gen8_set_dst(brw, inst, brw_ip_reg()); - gen8_set_src0(brw, inst, brw_ip_reg()); - gen8_set_src1(brw, inst, brw_imm_d(0)); + gen8_set_src0(brw, inst, brw_imm_d(0)); gen8_set_exec_size(inst, default_state.exec_size); return inst; } @@ -601,8 +602,7 @@ gen8_generator::WHILE() gen8_instruction *while_inst = next_inst(BRW_OPCODE_WHILE); gen8_set_dst(brw, while_inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - gen8_set_src0(brw, while_inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - gen8_set_src1(brw, while_inst, brw_imm_ud(0)); + gen8_set_src0(brw, while_inst, brw_imm_d(0)); gen8_set_jip(while_inst, 16 * (do_inst - while_inst)); gen8_set_exec_size(while_inst, default_state.exec_size); @@ -614,7 +614,7 @@ gen8_generator::HALT() { gen8_instruction *inst = next_inst(BRW_OPCODE_HALT); gen8_set_dst(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); - gen8_set_src0(brw, inst, retype(brw_null_reg(), BRW_REGISTER_TYPE_D)); + gen8_set_src0(brw, inst, brw_imm_d(0)); gen8_set_exec_size(inst, default_state.exec_size); gen8_set_mask_control(inst, BRW_MASK_DISABLE); return inst; |