BranchCommit messageAuthorAge
21.2docs: add sha256 sums for 21.2.6 relnotesDylan Baker7 months
21.3docs Add sha256 sums for 21.3.9Dylan Baker3 weeks
22.0docs: update sha256 for 22.0.5Dylan Baker4 weeks
22.1docs: add sha256sum to 22.1.2 notesDylan Baker12 days
mainzink: delete zink_resource_object::dt_has_dataMike Blumenkrantz3 hours
marge_bot_batch_merge_jobir3: Assert that we cannot have enough concurrent waves for CS with barrierDanylo Piliaiev6 months
staging/21.2spirv: run nir_copy_prop before nir_rematerialize_derefs_in_use_blocks_implRhys Perry7 months
staging/21.3docs Add sha256 sums for 21.3.9Dylan Baker3 weeks
staging/22.0aco: fix spilling of phis without temp operandsDaniel Schürmann4 weeks
staging/22.1intel/compiler: adjust task payload offsets as late as possibleMarcin Ślusarz14 hours
mesa-22.1.2commit a037d8e199...Dylan Baker12 days
mesa-21.3.9commit 78c96ae5b6...Dylan Baker3 weeks
mesa-22.0.5commit 18f91b5895...Dylan Baker4 weeks
mesa-22.1.1commit a730b834b0...Dylan Baker4 weeks
mesa-22.0.4commit a8194a9311...Dylan Baker6 weeks
mesa-22.1.0commit 01113c2eaa...Dylan Baker6 weeks
mesa-22.1.0-rc5commit 6fade22da9...Dylan Baker7 weeks
mesa-22.0.3commit 58ad6e52d1...Dylan Baker8 weeks
mesa-22.1.0-rc4commit fffad80496...Dylan Baker8 weeks
mesa-22.1.0-rc3commit 53fe3ea095...Dylan Baker2 months
AgeCommit messageAuthorFilesLines
2018-12-05Update version to 18.3.0-rc6mesa-18.3.0-rc6Emil Velikov1-1/+1
2018-12-05virgl: don't mark buffers as unclean after a writeGurchetan Singh2-1/+10
2018-12-05virgl: avoid large inline transfersGurchetan Singh1-1/+5
2018-12-05virgl: quadruple command buffer sizeGurchetan Singh1-1/+1
2018-12-05drisw: Use separate drisw_loader_funcs for shmMichal Srb1-3/+11
2018-12-05gallium: Constify drisw_loader_funcs structMichal Srb4-5/+5
2018-12-05radv: wait on the high 32 bits of timestamp queriesSamuel Pitoiset1-2/+5
2018-12-05anv/query: flush render target before copying resultsLionel Landwerlin5-0/+32
2018-12-05radv: Flush before vkCmdWriteTimestamp() if neededAlex Smith1-11/+19
2018-12-05radv: rework the TC-compat HTILE hardware bug with COND_EXECSamuel Pitoiset3-28/+81